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org.lwjgl.vulkan.KHRSynchronization2 Maven / Gradle / Ivy

/*
 * Copyright LWJGL. All rights reserved.
 * License terms: https://www.lwjgl.org/license
 * MACHINE GENERATED FILE, DO NOT EDIT
 */
package org.lwjgl.vulkan;

import javax.annotation.*;

import java.nio.*;

import org.lwjgl.system.*;

import static org.lwjgl.system.Checks.*;
import static org.lwjgl.system.JNI.*;
import static org.lwjgl.system.MemoryUtil.*;

/**
 * This extension modifies the original core synchronization APIs to simplify the interface and improve usability of these APIs. It also adds new pipeline stage and access flag types that extend into the 64-bit range, as we have run out within the 32-bit range. The new flags are identical to the old values within the 32-bit range, with new stages and bits beyond that.
 * 
 * 
Pipeline stages and access flags are now specified together in memory barrier structures, making the connection between the two more obvious. Additionally, scoping the pipeline stages into the barrier structs allows the use of the {@code MEMORY_READ} and {@code MEMORY_WRITE} flags without sacrificing precision. The per-stage access flags should be used to disambiguate specific accesses in a given stage or set of stages - for instance, between uniform reads and sampling operations.
 * 
 * 
Layout transitions have been simplified as well; rather than requiring a different set of layouts for depth/stencil/color attachments, there are generic {@link #VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR} and {@link #VK_IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR} layouts which are contextually applied based on the image format. For example, for a depth format image, {@link #VK_IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR} is equivalent to {@link KHRSeparateDepthStencilLayouts#VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL_KHR IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL_KHR}. {@link #VK_IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR} also functionally replaces {@link VK10#VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL}.
 * 
 * 
Events are now more efficient, because they include memory dependency information when you set them on the device. Previously, this information was only known when waiting on an event, so the dependencies could not be satisfied until the wait occurred. That sometimes meant stalling the pipeline when the wait occurred. The new API provides enough information for implementations to satisfy these dependencies in parallel with other tasks.
 * 
 * 
Queue submission has been changed to wrap command buffers and semaphores in extensible structures, which incorporate changes from Vulkan 1.1, {@link KHRDeviceGroup VK_KHR_device_group}, and {@link KHRTimelineSemaphore VK_KHR_timeline_semaphore}. This also adds a pipeline stage to the semaphore signal operation, mirroring the existing pipeline stage specification for wait operations.
 * 
 * 
Other miscellaneous changes include:
 * 
 * 

 * 
Events can now be specified as interacting only with the device, allowing more efficient access to the underlying object.
 * 
Image memory barriers that do not perform an image layout transition can be specified by setting {@code oldLayout} equal to {@code newLayout}.
 * 
 * 

 * 
E.g. the old and new layout can both be set to {@link VK10#VK_IMAGE_LAYOUT_UNDEFINED IMAGE_LAYOUT_UNDEFINED}, without discarding data in the image.
 * 
 * 
 * 
Queue family ownership transfer parameters are simplified in some cases.
 * 
Where two synchronization commands need to be matched up (queue transfer operations, events), the dependency information specified in each place must now match completely for consistency.
 * 
Extensions with commands or functions with a {@code VkPipelineStageFlags} or {@code VkPipelineStageFlagBits} parameter have had those APIs replaced with equivalents using {@code VkPipelineStageFlags2KHR}.
 * 
The new event and barrier interfaces are now more extensible for future changes.
 * 
Relevant pipeline stage masks can now be specified as empty with the new {@link #VK_PIPELINE_STAGE_NONE_KHR PIPELINE_STAGE_NONE_KHR} and {@link #VK_PIPELINE_STAGE_2_NONE_KHR PIPELINE_STAGE_2_NONE_KHR} values.
 * 
{@link VkMemoryBarrier2KHR} can be chained to {@link VkSubpassDependency2}, overriding the original 32-bit stage and access masks.
 * 
 * 
 * 
Examples
 * 
 * 
See https://github.com/KhronosGroup/Vulkan-Docs/wiki/Synchronization-Examples
 * 
 * 
VK_KHR_synchronization2
 * 
 * 

 * 
Name String
 * 
{@code VK_KHR_synchronization2}
 * 
Extension Type
 * 
Device extension
 * 
Registered Extension Number
 * 
315
 * 
Revision
 * 
1
 * 
Extension and Version Dependencies
 * 

 * 
Requires Vulkan 1.0
 * 
Requires {@link KHRGetPhysicalDeviceProperties2 VK_KHR_get_physical_device_properties2}
 * 
 * 
Contact
 * 

 * 
Tobias Hector tobski
 * 
 * 
 * 
 * 
Other Extension Metadata
 * 
 * 

 * 
Last Modified Date
 * 
2020-12-03
 * 
Interactions and External Dependencies
 * 

 * 
Interacts with {@link KHRCreateRenderpass2 VK_KHR_create_renderpass2}
 * 
 * 
Contributors
 * 

 * 
Tobias Hector
 * 
 * 
 */
public class KHRSynchronization2 {

    /** The extension specification version. */
    public static final int VK_KHR_SYNCHRONIZATION_2_SPEC_VERSION = 1;

    /** The extension name. */
    public static final String VK_KHR_SYNCHRONIZATION_2_EXTENSION_NAME = "VK_KHR_synchronization2";

    /**
     * Extends {@code VkStructureType}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_STRUCTURE_TYPE_MEMORY_BARRIER_2_KHR STRUCTURE_TYPE_MEMORY_BARRIER_2_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2_KHR STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2_KHR STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_DEPENDENCY_INFO_KHR STRUCTURE_TYPE_DEPENDENCY_INFO_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_SUBMIT_INFO_2_KHR STRUCTURE_TYPE_SUBMIT_INFO_2_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_SEMAPHORE_SUBMIT_INFO_KHR STRUCTURE_TYPE_SEMAPHORE_SUBMIT_INFO_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_COMMAND_BUFFER_SUBMIT_INFO_KHR STRUCTURE_TYPE_COMMAND_BUFFER_SUBMIT_INFO_KHR}
     * 
{@link #VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES_KHR STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES_KHR}
     * 
     */
    public static final int
        VK_STRUCTURE_TYPE_MEMORY_BARRIER_2_KHR                           = 1000314000,
        VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2_KHR                    = 1000314001,
        VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2_KHR                     = 1000314002,
        VK_STRUCTURE_TYPE_DEPENDENCY_INFO_KHR                            = 1000314003,
        VK_STRUCTURE_TYPE_SUBMIT_INFO_2_KHR                              = 1000314004,
        VK_STRUCTURE_TYPE_SEMAPHORE_SUBMIT_INFO_KHR                      = 1000314005,
        VK_STRUCTURE_TYPE_COMMAND_BUFFER_SUBMIT_INFO_KHR                 = 1000314006,
        VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES_KHR = 1000314007;

    /** Extends {@code VkEventCreateFlagBits}. */
    public static final int VK_EVENT_CREATE_DEVICE_ONLY_BIT_KHR = 0x1;

    /**
     * Extends {@code VkImageLayout}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR}
     * 
{@link #VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR}
     * 
     */
    public static final int
        VK_IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR  = 1000314000,
        VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR = 1000314001;

    /** Extends {@code VkPipelineStageFlagBits}. */
    public static final int VK_PIPELINE_STAGE_NONE_KHR = 0;

    /** Extends {@code VkAccessFlagBits}. */
    public static final int VK_ACCESS_NONE_KHR = 0;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT = 0x1000000L;

    /**
     * Extends {@code VkAccessFlagBits2KHR}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT}
     * 
{@link #VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT}
     * 
{@link #VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT}
     * 
     */
    public static final long
        VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT         = 0x2000000L,
        VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT  = 0x4000000L,
        VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT = 0x8000000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT = 0x40000L;

    /** Extends {@code VkAccessFlagBits2KHR}. */
    public static final long VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT = 0x100000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV = 0x20000L;

    /**
     * Extends {@code VkAccessFlagBits2KHR}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV}
     * 
{@link #VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV}
     * 
     */
    public static final long
        VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV  = 0x20000L,
        VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV = 0x40000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR = 0x400000L;

    /** Extends {@code VkAccessFlagBits2KHR}. */
    public static final long VK_ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR = 0x800000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV = 0x400000L;

    /** Extends {@code VkAccessFlagBits2KHR}. */
    public static final long VK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV = 0x800000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR = 0x2000000L;

    /**
     * Extends {@code VkAccessFlagBits2KHR}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR}
     * 
{@link #VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR}
     * 
     */
    public static final long
        VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR  = 0x200000L,
        VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR = 0x400000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR = 0x200000L;

    /**
     * Extends {@code VkPipelineStageFlagBits2KHR}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_NV PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_NV}
     * 
{@link #VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_NV PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_NV}
     * 
     */
    public static final long
        VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_NV           = 0x200000L,
        VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_NV = 0x2000000L;

    /**
     * Extends {@code VkAccessFlagBits2KHR}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_NV ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_NV}
     * 
{@link #VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_NV ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_NV}
     * 
     */
    public static final long
        VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_NV  = 0x200000L,
        VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_NV = 0x400000L;

    /** Extends {@code VkPipelineStageFlagBits2KHR}. */
    public static final long VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT = 0x800000L;

    /** Extends {@code VkAccessFlagBits2KHR}. */
    public static final long VK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT = 0x1000000L;

    /** Extends {@code VkAccessFlagBits2KHR}. */
    public static final long VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT = 0x80000L;

    /**
     * Extends {@code VkPipelineStageFlagBits2KHR}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}
     * 
{@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}
     * 
     */
    public static final long
        VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV = 0x80000L,
        VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV = 0x100000L;

    /**
     * Extends {@code VkStructureType}.
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_STRUCTURE_TYPE_QUEUE_FAMILY_CHECKPOINT_PROPERTIES_2_NV STRUCTURE_TYPE_QUEUE_FAMILY_CHECKPOINT_PROPERTIES_2_NV}
     * 
{@link #VK_STRUCTURE_TYPE_CHECKPOINT_DATA_2_NV STRUCTURE_TYPE_CHECKPOINT_DATA_2_NV}
     * 
     */
    public static final int
        VK_STRUCTURE_TYPE_QUEUE_FAMILY_CHECKPOINT_PROPERTIES_2_NV = 1000314008,
        VK_STRUCTURE_TYPE_CHECKPOINT_DATA_2_NV                    = 1000314009;

    /**
     * VkPipelineStageFlagBits2KHR - Pipeline stage flags for VkPipelineStageFlags2KHR
     * 
     * 
Description
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_NONE_KHR PIPELINE_STAGE_2_NONE_KHR} specifies no stages of execution.
     * 
{@link #VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR} specifies the stage of the pipeline where indirect command parameters are consumed. This stage also includes reading commands written by {@link NVDeviceGeneratedCommands#vkCmdPreprocessGeneratedCommandsNV CmdPreprocessGeneratedCommandsNV}.
     * 
{@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV} specifies the task shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV} specifies the mesh shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR} specifies the stage of the pipeline where index buffers are consumed.
     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR} specifies the stage of the pipeline where vertex buffers are consumed.
     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR} is equivalent to the logical OR of:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR}
     * 
     * 
     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR} specifies the vertex shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR} specifies the tessellation control shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR} specifies the tessellation evaluation shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR} specifies the geometry shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR} is equivalent to specifying all supported pre-rasterization shader stages:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}
     * 
{@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}
     * 
     * 
     * 
{@link #VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR} specifies the fragment shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR} specifies the stage of the pipeline where early fragment tests (depth and stencil tests before fragment shading) are performed. This stage also includes subpass load operations for framebuffer attachments with a depth/stencil format.
     * 
{@link #VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR} specifies the stage of the pipeline where late fragment tests (depth and stencil tests after fragment shading) are performed. This stage also includes subpass store operations for framebuffer attachments with a depth/stencil format.
     * 
{@link #VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR} specifies the stage of the pipeline after blending where the final color values are output from the pipeline. This stage also includes subpass load and store operations and multisample resolve operations for framebuffer attachments with a color or depth/stencil format.
     * 
{@link #VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT_KHR PIPELINE_STAGE_2_COMPUTE_SHADER_BIT_KHR} specifies the compute shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_HOST_BIT_KHR PIPELINE_STAGE_2_HOST_BIT_KHR} specifies a pseudo-stage indicating execution on the host of reads/writes of device memory. This stage is not invoked by any commands recorded in a command buffer.
     * 
{@link #VK_PIPELINE_STAGE_2_COPY_BIT_KHR PIPELINE_STAGE_2_COPY_BIT_KHR} specifies the execution of all copy commands, including {@link VK10#vkCmdCopyQueryPoolResults CmdCopyQueryPoolResults}.
     * 
{@link #VK_PIPELINE_STAGE_2_BLIT_BIT_KHR PIPELINE_STAGE_2_BLIT_BIT_KHR} specifies the execution of {@link VK10#vkCmdBlitImage CmdBlitImage}.
     * 
{@link #VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR PIPELINE_STAGE_2_RESOLVE_BIT_KHR} specifies the execution of {@link VK10#vkCmdResolveImage CmdResolveImage}.
     * 
{@link #VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR PIPELINE_STAGE_2_CLEAR_BIT_KHR} specifies the execution of clear commands, with the exception of {@link VK10#vkCmdClearAttachments CmdClearAttachments}.
     * 
{@link #VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR} is equivalent to specifying all of:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_COPY_BIT_KHR PIPELINE_STAGE_2_COPY_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_BLIT_BIT_KHR PIPELINE_STAGE_2_BLIT_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR PIPELINE_STAGE_2_RESOLVE_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR PIPELINE_STAGE_2_CLEAR_BIT_KHR}
     * 
     * 
     * 
{@link #VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR} specifies the execution of the ray tracing shader stages.
     * 
{@link #VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR} specifies the execution of acceleration structure commands.
     * 
{@link #VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR} specifies the execution of all graphics pipeline stages, and is equivalent to the logical OR of:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}
     * 
{@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}
     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR}
     * 
{@link #VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT}
     * 
{@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT}
     * 
{@link #VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV}
     * 
{@link #VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT}
     * 
{@link HUAWEIInvocationMask#VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI}
     * 
     * 
     * 
{@link #VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR} specifies all operations performed by all commands supported on the queue it is used with.
     * 
{@link #VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT} specifies the stage of the pipeline where the predicate of conditional rendering is consumed.
     * 
{@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT} specifies the stage of the pipeline where vertex attribute output values are written to the transform feedback buffers.
     * 
{@link #VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV} specifies the stage of the pipeline where device-side generation of commands via {@link NVDeviceGeneratedCommands#vkCmdPreprocessGeneratedCommandsNV CmdPreprocessGeneratedCommandsNV} is handled.
     * 
{@link #VK_PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR} specifies the stage of the pipeline where the fragment shading rate attachment or shading rate image is read to determine the fragment shading rate for portions of a rasterized primitive.
     * 
{@link #VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT} specifies the stage of the pipeline where the fragment density map is read to generate the fragment areas.
     * 
{@link HUAWEIInvocationMask#VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI} specifies the stage of the pipeline where the invocation mask image is read by the implementation to optimize the ray dispatch.
     * 
{@link KHRVideoDecodeQueue#VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR} specifies the stage of the pipeline where video decode operation are performed.
     * 
{@link KHRVideoEncodeQueue#VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR} specifies the stage of the pipeline where video encode operation are performed.
     * 
{@link HUAWEISubpassShading#VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI} specifies the subpass shading shader stage.
     * 
{@link #VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR} is equivalent to {@link #VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR} with {@code VkAccessFlags2KHR} set to 0 when specified in the second synchronization scope, but equivalent to {@link #VK_PIPELINE_STAGE_2_NONE_KHR PIPELINE_STAGE_2_NONE_KHR} in the first scope.
     * 
{@link #VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR} is equivalent to {@link #VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR} with {@code VkAccessFlags2KHR} set to 0 when specified in the first synchronization scope, but equivalent to {@link #VK_PIPELINE_STAGE_2_NONE_KHR PIPELINE_STAGE_2_NONE_KHR} in the second scope.
     * 
     * 
     * 
Note
     * 
     * 
The {@code TOP} and {@code BOTTOM} pipeline stages are deprecated, and applications should prefer {@link #VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR} and {@link #VK_PIPELINE_STAGE_2_NONE_KHR PIPELINE_STAGE_2_NONE_KHR}.
     * 
     * 
     * 
Note
     * 
     * 
The {@code VkPipelineStageFlags2KHR} bitmask goes beyond the 31 individual bit flags allowable within a C99 enum, which is how {@code VkPipelineStageFlagBits} is defined. The first 31 values are common to both, and are interchangeable.
     * 
     * 
     * 
Enum values:
     * 
     * 

     * 
{@link #VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR PIPELINE_STAGE_2_TRANSFER_BIT_KHR}
     * 
     */
    public static final long
        VK_PIPELINE_STAGE_2_NONE_KHR                               = 0L,
        VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR                    = 0x1L,
        VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR                  = 0x2L,
        VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR                   = 0x4L,
        VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR                  = 0x8L,
        VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR    = 0x10L,
        VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR = 0x20L,
        VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR                = 0x40L,
        VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR                = 0x80L,
        VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR           = 0x100L,
        VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR            = 0x200L,
        VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR        = 0x400L,
        VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT_KHR                 = 0x800L,
        VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR                   = 0x1000L,
        VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR                       = 0x1000L,
        VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR                 = 0x2000L,
        VK_PIPELINE_STAGE_2_HOST_BIT_KHR                           = 0x4000L,
        VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR                   = 0x8000L,
        VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR                   = 0x10000L,
        VK_PIPELINE_STAGE_2_COPY_BIT_KHR                           = 0x100000000L,
        VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR                        = 0x200000000L,
        VK_PIPELINE_STAGE_2_BLIT_BIT_KHR                           = 0x400000000L,
        VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR                          = 0x800000000L,
        VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR                    = 0x1000000000L,
        VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR         = 0x2000000000L,
        VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR      = 0x4000000000L;

    /**
     * VkAccessFlagBits2KHR - Access flags for VkAccessFlags2KHR
     * 
     * 
Description
     * 
     * 

     * 
{@link #VK_ACCESS_2_NONE_KHR ACCESS_2_NONE_KHR} specifies no accesses.
     * 
{@link #VK_ACCESS_2_MEMORY_READ_BIT_KHR ACCESS_2_MEMORY_READ_BIT_KHR} specifies all read accesses. It is always valid in any access mask, and is treated as equivalent to setting all {@code READ} access flags that are valid where it is used.
     * 
{@link #VK_ACCESS_2_MEMORY_WRITE_BIT_KHR ACCESS_2_MEMORY_WRITE_BIT_KHR} specifies all write accesses. It is always valid in any access mask, and is treated as equivalent to setting all {@code WRITE} access flags that are valid where it is used.
     * 
{@link #VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR} specifies read access to command data read from indirect buffers as part of an indirect build, trace, drawing or dispatch command. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_INDEX_READ_BIT_KHR ACCESS_2_INDEX_READ_BIT_KHR} specifies read access to an index buffer as part of an indexed drawing command, bound by {@link VK10#vkCmdBindIndexBuffer CmdBindIndexBuffer}. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR} specifies read access to a vertex buffer as part of a drawing command, bound by {@link VK10#vkCmdBindVertexBuffers CmdBindVertexBuffers}. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_UNIFORM_READ_BIT_KHR ACCESS_2_UNIFORM_READ_BIT_KHR} specifies read access to a uniform buffer in any shader pipeline stage.
     * 
{@link #VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR} specifies read access to an input attachment within a render pass during subpass shading or fragment shading. Such access occurs in the {@link HUAWEISubpassShading#VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI} or {@link #VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR} specifies read access to a uniform texel buffer or sampled image in any shader pipeline stage.
     * 
{@link #VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR ACCESS_2_SHADER_STORAGE_READ_BIT_KHR} specifies read access to a storage buffer, physical storage buffer, storage texel buffer, or storage image in any shader pipeline stage.
     * 
{@link #VK_ACCESS_2_SHADER_READ_BIT_KHR ACCESS_2_SHADER_READ_BIT_KHR} specifies read access to a shader binding table in any shader pipeline. In addition, it is equivalent to the logical OR of:
     * 
     * 

     * 
{@link #VK_ACCESS_2_UNIFORM_READ_BIT_KHR ACCESS_2_UNIFORM_READ_BIT_KHR}
     * 
{@link #VK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR}
     * 
{@link #VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR ACCESS_2_SHADER_STORAGE_READ_BIT_KHR}
     * 
     * 
     * 
{@link #VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR} specifies write access to a storage buffer, physical storage buffer, storage texel buffer, or storage image in any shader pipeline stage.
     * 
{@link #VK_ACCESS_2_SHADER_WRITE_BIT_KHR ACCESS_2_SHADER_WRITE_BIT_KHR} is equivalent to {@link #VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR}.
     * 
{@link #VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR} specifies read access to a color attachment, such as via blending, logic operations, or via certain subpass load operations. It does not include advanced blend operations. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR} specifies write access to a color, resolve, or depth/stencil resolve attachment during a render pass or via certain subpass load and store operations. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR} specifies read access to a depth/stencil attachment, via depth or stencil operations or via certain subpass load operations. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR} or {@link #VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR} pipeline stages.
     * 
{@link #VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR} specifies write access to a depth/stencil attachment, via depth or stencil operations or via certain subpass load and store operations. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR} or {@link #VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR} pipeline stages.
     * 
{@link #VK_ACCESS_2_TRANSFER_READ_BIT_KHR ACCESS_2_TRANSFER_READ_BIT_KHR} specifies read access to an image or buffer in a copy operation. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COPY_BIT_KHR PIPELINE_STAGE_2_COPY_BIT_KHR}, {@link #VK_PIPELINE_STAGE_2_BLIT_BIT_KHR PIPELINE_STAGE_2_BLIT_BIT_KHR}, or {@link #VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR PIPELINE_STAGE_2_RESOLVE_BIT_KHR} pipeline stages.
     * 
{@link #VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR ACCESS_2_TRANSFER_WRITE_BIT_KHR} specifies write access to an image or buffer in a clear or copy operation. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COPY_BIT_KHR PIPELINE_STAGE_2_COPY_BIT_KHR}, {@link #VK_PIPELINE_STAGE_2_BLIT_BIT_KHR PIPELINE_STAGE_2_BLIT_BIT_KHR}, {@link #VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR PIPELINE_STAGE_2_CLEAR_BIT_KHR}, or {@link #VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR PIPELINE_STAGE_2_RESOLVE_BIT_KHR} pipeline stages.
     * 
{@link #VK_ACCESS_2_HOST_READ_BIT_KHR ACCESS_2_HOST_READ_BIT_KHR} specifies read access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_HOST_BIT_KHR PIPELINE_STAGE_2_HOST_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_HOST_WRITE_BIT_KHR ACCESS_2_HOST_WRITE_BIT_KHR} specifies write access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_HOST_BIT_KHR PIPELINE_STAGE_2_HOST_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT} specifies read access to a predicate as part of conditional rendering. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT} pipeline stage.
     * 
{@link #VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT} specifies write access to a transform feedback buffer made when transform feedback is active. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT} pipeline stage.
     * 
{@link #VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT} specifies read access to a transform feedback counter buffer which is read when {@link EXTTransformFeedback#vkCmdBeginTransformFeedbackEXT CmdBeginTransformFeedbackEXT} executes. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT} pipeline stage.
     * 
{@link #VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT} specifies write access to a transform feedback counter buffer which is written when {@link EXTTransformFeedback#vkCmdEndTransformFeedbackEXT CmdEndTransformFeedbackEXT} executes. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT} pipeline stage.
     * 
{@link #VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV} specifies reads from buffer inputs to {@link NVDeviceGeneratedCommands#vkCmdPreprocessGeneratedCommandsNV CmdPreprocessGeneratedCommandsNV}. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV} pipeline stage.
     * 
{@link #VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV} specifies writes to the target command buffer preprocess outputs. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV} pipeline stage.
     * 
{@link #VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT} specifies read access to color attachments, including advanced blend operations. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR} pipeline stage.
     * 
{@link HUAWEIInvocationMask#VK_ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI} specifies read access to a invocation mask image in the {@link HUAWEIInvocationMask#VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI} pipeline stage.
     * 
{@link #VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR} specifies read access to an acceleration structure as part of a trace, build, or copy command, or to an acceleration structure scratch buffer as part of a build command. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR} pipeline stage or {@link #VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR} specifies write access to an acceleration structure or acceleration structure scratch buffer as part of a build or copy command. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT} specifies read access to a fragment density map attachment during dynamic fragment density map operations. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT} pipeline stage.
     * 
{@link #VK_ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR} specifies read access to a fragment shading rate attachment during rasterization. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR} pipeline stage.
     * 
{@link #VK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV} specifies read access to a shading rate image during rasterization. Such access occurs in the {@link #VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV} pipeline stage. It is equivalent to {@link #VK_ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR}.
     * 
{@link KHRVideoDecodeQueue#VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR ACCESS_2_VIDEO_DECODE_READ_BIT_KHR} specifies read access to an image or buffer resource as part of a video decode operation. Such access occurs in the {@link KHRVideoDecodeQueue#VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR} pipeline stage.
     * 
{@link KHRVideoDecodeQueue#VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR} specifies write access to an image or buffer resource as part of a video decode operation. Such access occurs in the {@link KHRVideoDecodeQueue#VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR} pipeline stage.
     * 
{@link KHRVideoEncodeQueue#VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR} specifies read access to an image or buffer resource as part of a video encode operation. Such access occurs in the {@link KHRVideoEncodeQueue#VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR} pipeline stage.
     * 
{@link KHRVideoEncodeQueue#VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR} specifies write access to an image or buffer resource as part of a video encode operation. Such access occurs in the {@link KHRVideoEncodeQueue#VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR} pipeline stage.
     * 
     * 
     * 
Note
     * 
     * 
In situations where an application wishes to select all access types for a given set of pipeline stages, {@link #VK_ACCESS_2_MEMORY_READ_BIT_KHR ACCESS_2_MEMORY_READ_BIT_KHR} or {@link #VK_ACCESS_2_MEMORY_WRITE_BIT_KHR ACCESS_2_MEMORY_WRITE_BIT_KHR} can be used. This is particularly useful when specifying stages that only have a single access type.
     * 
     * 
     * 
Note
     * 
     * 
The {@code VkAccessFlags2KHR} bitmask goes beyond the 31 individual bit flags allowable within a C99 enum, which is how {@code VkAccessFlagBits} is defined. The first 31 values are common to both, and are interchangeable.
     * 
     */
    public static final long
        VK_ACCESS_2_NONE_KHR                               = 0L,
        VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR          = 0x1L,
        VK_ACCESS_2_INDEX_READ_BIT_KHR                     = 0x2L,
        VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR          = 0x4L,
        VK_ACCESS_2_UNIFORM_READ_BIT_KHR                   = 0x8L,
        VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR          = 0x10L,
        VK_ACCESS_2_SHADER_READ_BIT_KHR                    = 0x20L,
        VK_ACCESS_2_SHADER_WRITE_BIT_KHR                   = 0x40L,
        VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR          = 0x80L,
        VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR         = 0x100L,
        VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR  = 0x200L,
        VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR = 0x400L,
        VK_ACCESS_2_TRANSFER_READ_BIT_KHR                  = 0x800L,
        VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR                 = 0x1000L,
        VK_ACCESS_2_HOST_READ_BIT_KHR                      = 0x2000L,
        VK_ACCESS_2_HOST_WRITE_BIT_KHR                     = 0x4000L,
        VK_ACCESS_2_MEMORY_READ_BIT_KHR                    = 0x8000L,
        VK_ACCESS_2_MEMORY_WRITE_BIT_KHR                   = 0x10000L,
        VK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR            = 0x100000000L,
        VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR            = 0x200000000L,
        VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR           = 0x400000000L;

    /**
     * VkSubmitFlagBitsKHR - Bitmask specifying behavior of a submission
     * 
     * 
Description
     * 
     * 

     * 
{@link #VK_SUBMIT_PROTECTED_BIT_KHR SUBMIT_PROTECTED_BIT_KHR} specifies that this batch is a protected submission.
     * 
     */
    public static final int VK_SUBMIT_PROTECTED_BIT_KHR = 0x1;

    protected KHRSynchronization2() {
        throw new UnsupportedOperationException();
    }

    // --- [ vkCmdSetEvent2KHR ] ---

    /** Unsafe version of: {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} */
    public static void nvkCmdSetEvent2KHR(VkCommandBuffer commandBuffer, long event, long pDependencyInfo) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdSetEvent2KHR;
        if (CHECKS) {
            check(__functionAddress);
            VkDependencyInfoKHR.validate(pDependencyInfo);
        }
        callPJPV(commandBuffer.address(), event, pDependencyInfo, __functionAddress);
    }

    /**
     * Set an event object to signaled state.
     * 
     * 
C Specification
     * 
     * 
To signal an event from a device, call:
     * 
     * 

     * void vkCmdSetEvent2KHR(
     *     VkCommandBuffer                             commandBuffer,
     *     VkEvent                                     event,
     *     const VkDependencyInfoKHR*                  pDependencyInfo);
     * 
     * 
Description
     * 
     * 
When {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} is submitted to a queue, it defines the first half of memory dependencies defined by {@code pDependencyInfo}, as well as an event signal operation which sets the event to the signaled state. A memory dependency is defined between the event signal operation and commands that occur earlier in submission order.
     * 
     * 
The first synchronization scope and access scope are defined by the union of all the memory dependencies defined by {@code pDependencyInfo}, and are applied to all operations that occur earlier in submission order. Queue family ownership transfers and image layout transitions defined by {@code pDependencyInfo} are also included in the first scopes.
     * 
     * 
The second synchronization scope includes only the event signal operation, and any queue family ownership transfers and image layout transitions defined by {@code pDependencyInfo}.
     * 
     * 
The second access scope includes only queue family ownership transfers and image layout transitions.
     * 
     * 
Future {@link #vkCmdWaitEvents2KHR CmdWaitEvents2KHR} commands rely on all values of each element in {@code pDependencyInfo} matching exactly with those used to signal the corresponding event. {@link VK10#vkCmdWaitEvents CmdWaitEvents} must not be used to wait on the result of a signal operation defined by {@code vkCmdSetEvent2KHR}.
     * 
     * 
Note
     * 
     * 
The extra information provided by {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} compared to {@link VK10#vkCmdSetEvent CmdSetEvent} allows implementations to more efficiently schedule the operations required to satisfy the requested dependencies. With {@link VK10#vkCmdSetEvent CmdSetEvent}, the full dependency information is not known until {@link VK10#vkCmdWaitEvents CmdWaitEvents} is recorded, forcing implementations to insert the required operations at that point and not before.
     * 
     * 
     * 
If {@code event} is already in the signaled state when {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} is executed on the device, then {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} has no effect, no event signal operation occurs, and no dependency is generated.
     * 
     * 
Valid Usage
     * 
     * 

     * 
The {@code synchronization2} feature must be enabled
     * 
The {@code dependencyFlags} member of {@code pDependencyInfo} must be 0
     * 
The current device mask of {@code commandBuffer} must include exactly one physical device
     * 
The {@code srcStageMask} member of any element of the {@code pMemoryBarriers}, {@code pBufferMemoryBarriers}, or {@code pImageMemoryBarriers} members of {@code pDependencyInfo} must only include pipeline stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
The {@code dstStageMask} member of any element of the {@code pMemoryBarriers}, {@code pBufferMemoryBarriers}, or {@code pImageMemoryBarriers} members of {@code pDependencyInfo} must only include pipeline stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code commandBuffer} must be a valid {@code VkCommandBuffer} handle
     * 
{@code event} must be a valid {@code VkEvent} handle
     * 
{@code pDependencyInfo} must be a valid pointer to a valid {@link VkDependencyInfoKHR} structure
     * 
{@code commandBuffer} must be in the recording state
     * 
The {@code VkCommandPool} that {@code commandBuffer} was allocated from must support graphics, or compute operations
     * 
This command must only be called outside of a render pass instance
     * 
Both of {@code commandBuffer}, and {@code event} must have been created, allocated, or retrieved from the same {@code VkDevice}
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code commandBuffer} must be externally synchronized
     * 
Host access to the {@code VkCommandPool} that {@code commandBuffer} was allocated from must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
Primary Secondary
Outside
Graphics Compute
     * 
     * 
See Also
     * 
     * 
{@link VkDependencyInfoKHR}
     *
     * @param commandBuffer   the command buffer into which the command is recorded.
     * @param event           the event that will be signaled.
     * @param pDependencyInfo a pointer to a {@link VkDependencyInfoKHR} structure defining the first scopes of this operation.
     */
    public static void vkCmdSetEvent2KHR(VkCommandBuffer commandBuffer, @NativeType("VkEvent") long event, @NativeType("VkDependencyInfoKHR const *") VkDependencyInfoKHR pDependencyInfo) {
        nvkCmdSetEvent2KHR(commandBuffer, event, pDependencyInfo.address());
    }

    // --- [ vkCmdResetEvent2KHR ] ---

    /**
     * Reset an event object to non-signaled state.
     * 
     * 
C Specification
     * 
     * 
To unsignal the event from a device, call:
     * 
     * 

     * void vkCmdResetEvent2KHR(
     *     VkCommandBuffer                             commandBuffer,
     *     VkEvent                                     event,
     *     VkPipelineStageFlags2KHR                    stageMask);
     * 
     * 
Description
     * 
     * 
When {@link #vkCmdResetEvent2KHR CmdResetEvent2KHR} is submitted to a queue, it defines an execution dependency on commands that were submitted before it, and defines an event unsignal operation which resets the event to the unsignaled state.
     * 
     * 
The first synchronization scope includes all commands that occur earlier in submission order. The synchronization scope is limited to operations by {@code stageMask} or stages that are logically earlier than {@code stageMask}.
     * 
     * 
The second synchronization scope includes only the event unsignal operation.
     * 
     * 
If {@code event} is already in the unsignaled state when {@link #vkCmdResetEvent2KHR CmdResetEvent2KHR} is executed on the device, then this command has no effect, no event unsignal operation occurs, and no execution dependency is generated.
     * 
     * 
Valid Usage
     * 
     * 

     * 
If the geometry shaders feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR}
     * 
If the tessellation shaders feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR} or {@link #VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR}
     * 
If the conditional rendering feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT}
     * 
If the fragment density map feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT}
     * 
If the transform feedback feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT}
     * 
If the mesh shaders feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}
     * 
If the task shaders feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}
     * 
If the shading rate image feature is not enabled, {@code stageMask} must not contain {@link #VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV}
     * 
If the subpass shading feature is not enabled, {@code stageMask} must not contain {@link HUAWEISubpassShading#VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI}
     * 
If the invocation mask image feature is not enabled, {@code stageMask} must not contain {@link HUAWEIInvocationMask#VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI}
     * 
The {@code synchronization2} feature must be enabled
     * 
{@code stageMask} must not include {@link #VK_PIPELINE_STAGE_2_HOST_BIT_KHR PIPELINE_STAGE_2_HOST_BIT_KHR}
     * 
There must be an execution dependency between {@code vkCmdResetEvent2KHR} and the execution of any {@link VK10#vkCmdWaitEvents CmdWaitEvents} that includes {@code event} in its {@code pEvents} parameter
     * 
There must be an execution dependency between {@code vkCmdResetEvent2KHR} and the execution of any {@link #vkCmdWaitEvents2KHR CmdWaitEvents2KHR} that includes {@code event} in its {@code pEvents} parameter
     * 
{@code commandBuffer}’s current device mask must include exactly one physical device
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code commandBuffer} must be a valid {@code VkCommandBuffer} handle
     * 
{@code event} must be a valid {@code VkEvent} handle
     * 
{@code stageMask} must be a valid combination of {@code VkPipelineStageFlagBits2KHR} values
     * 
{@code stageMask} must not be 0
     * 
{@code commandBuffer} must be in the recording state
     * 
The {@code VkCommandPool} that {@code commandBuffer} was allocated from must support graphics, or compute operations
     * 
This command must only be called outside of a render pass instance
     * 
Both of {@code commandBuffer}, and {@code event} must have been created, allocated, or retrieved from the same {@code VkDevice}
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code commandBuffer} must be externally synchronized
     * 
Host access to the {@code VkCommandPool} that {@code commandBuffer} was allocated from must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
Primary Secondary
Outside
Graphics Compute
     *
     * @param commandBuffer the command buffer into which the command is recorded.
     * @param event         the event that will be unsignaled.
     * @param stageMask     a {@code VkPipelineStageFlags2KHR} mask of pipeline stages used to determine the first synchronization scope.
     */
    public static void vkCmdResetEvent2KHR(VkCommandBuffer commandBuffer, @NativeType("VkEvent") long event, @NativeType("VkPipelineStageFlags2KHR") long stageMask) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdResetEvent2KHR;
        if (CHECKS) {
            check(__functionAddress);
        }
        callPJJV(commandBuffer.address(), event, stageMask, __functionAddress);
    }

    // --- [ vkCmdWaitEvents2KHR ] ---

    /**
     * Unsafe version of: {@link #vkCmdWaitEvents2KHR CmdWaitEvents2KHR}
     *
     * @param eventCount the length of the {@code pEvents} array.
     */
    public static void nvkCmdWaitEvents2KHR(VkCommandBuffer commandBuffer, int eventCount, long pEvents, long pDependencyInfos) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdWaitEvents2KHR;
        if (CHECKS) {
            check(__functionAddress);
            Struct.validate(pDependencyInfos, eventCount, VkDependencyInfoKHR.SIZEOF, VkDependencyInfoKHR::validate);
        }
        callPPPV(commandBuffer.address(), eventCount, pEvents, pDependencyInfos, __functionAddress);
    }

    /**
     * Wait for one or more events.
     * 
     * 
C Specification
     * 
     * 
To wait for one or more events to enter the signaled state on a device, call:
     * 
     * 

     * void vkCmdWaitEvents2KHR(
     *     VkCommandBuffer                             commandBuffer,
     *     uint32_t                                    eventCount,
     *     const VkEvent*                              pEvents,
     *     const VkDependencyInfoKHR*                  pDependencyInfos);
     * 
     * 
Description
     * 
     * 
When {@code vkCmdWaitEvents2KHR} is submitted to a queue, it inserts memory dependencies according to the elements of {@code pDependencyInfos} and each corresponding element of {@code pEvents}. {@code vkCmdWaitEvents2KHR} must not be used to wait on event signal operations occurring on other queues, or signal operations execyted by {@link VK10#vkCmdSetEvent CmdSetEvent}.
     * 
     * 
The first synchronization scope and access scope of each memory dependency defined by any element i of {@code pDependencyInfos} are applied to operations that occurred earlier in submission order than the last event signal operation on element i of {@code pEvents}.
     * 
     * 
Signal operations for an event at index i are only included if:
     * 
     * 

     * 
The event was signaled by a {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} command that occurred earlier in submission order with a {@code dependencyInfo} parameter exactly equal to the element of {@code pDependencyInfos} at index i ; or
     * 
The event was created without {@link #VK_EVENT_CREATE_DEVICE_ONLY_BIT_KHR EVENT_CREATE_DEVICE_ONLY_BIT_KHR}, and the first synchronization scope defined by the element of {@code pDependencyInfos} at index i only includes host operations ({@link #VK_PIPELINE_STAGE_2_HOST_BIT_KHR PIPELINE_STAGE_2_HOST_BIT_KHR}).
     * 
     * 
     * 
The second synchronization scope and access scope of each memory dependency defined by any element i of {@code pDependencyInfos} are applied to operations that occurred later in submission order than {@code vkCmdWaitEvents2KHR}.
     * 
     * 
Note
     * 
     * 
{@link #vkCmdWaitEvents2KHR CmdWaitEvents2KHR} is used with {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} to define a memory dependency between two sets of action commands, roughly in the same way as pipeline barriers, but split into two commands such that work between the two may execute unhindered.
     * 
     * 
     * 
Note
     * 
     * 
Applications should be careful to avoid race conditions when using events. There is no direct ordering guarantee between {@code vkCmdSetEvent2KHR} and {@link #vkCmdResetEvent2KHR CmdResetEvent2KHR}, {@link VK10#vkCmdResetEvent CmdResetEvent}, or {@link VK10#vkCmdSetEvent CmdSetEvent}. Another execution dependency (e.g. a pipeline barrier or semaphore with {@link #VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR}) is needed to prevent such a race condition.
     * 
     * 
     * 
Valid Usage
     * 
     * 

     * 
The {@code synchronization2} feature must be enabled
     * 
Members of {@code pEvents} must not have been signaled by {@link VK10#vkCmdSetEvent CmdSetEvent}
     * 
For any element i of {@code pEvents}, if that event is signaled by {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR}, that command’s {@code dependencyInfo} parameter must be exactly equal to the ith element of {@code pDependencyInfos}
     * 
For any element i of {@code pEvents}, if that event is signaled by {@link VK10#vkSetEvent SetEvent}, barriers in the ith element of {@code pDependencyInfos} must include only host operations in their first synchronization scope
     * 
For any element i of {@code pEvents}, if barriers in the ith element of {@code pDependencyInfos} include only host operations, the ith element of {@code pEvents} must be signaled before {@link #vkCmdWaitEvents2KHR CmdWaitEvents2KHR} is executed
     * 
For any element i of {@code pEvents}, if barriers in the ith element of {@code pDependencyInfos} do not include host operations, the ith element of {@code pEvents} must be signaled by a corresponding {@link #vkCmdSetEvent2KHR CmdSetEvent2KHR} that occurred earlier in submission order
     * 
The {@code srcStageMask} member of any element of the {@code pMemoryBarriers}, {@code pBufferMemoryBarriers}, or {@code pImageMemoryBarriers} members of {@code pDependencyInfos} must either include only pipeline stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from, or include only {@link #VK_PIPELINE_STAGE_2_HOST_BIT_KHR PIPELINE_STAGE_2_HOST_BIT_KHR}
     * 
The {@code dstStageMask} member of any element of the {@code pMemoryBarriers}, {@code pBufferMemoryBarriers}, or {@code pImageMemoryBarriers} members of {@code pDependencyInfos} must only include pipeline stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
The {@code dependencyFlags} member of any element of {@code pDependencyInfo} must be 0
     * 
If {@code pEvents} includes one or more events that will be signaled by {@link VK10#vkSetEvent SetEvent} after {@code commandBuffer} has been submitted to a queue, then {@code vkCmdWaitEvents2KHR} must not be called inside a render pass instance
     * 
{@code commandBuffer}’s current device mask must include exactly one physical device
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code commandBuffer} must be a valid {@code VkCommandBuffer} handle
     * 
{@code pEvents} must be a valid pointer to an array of {@code eventCount} valid {@code VkEvent} handles
     * 
{@code pDependencyInfos} must be a valid pointer to an array of {@code eventCount} valid {@link VkDependencyInfoKHR} structures
     * 
{@code commandBuffer} must be in the recording state
     * 
The {@code VkCommandPool} that {@code commandBuffer} was allocated from must support graphics, or compute operations
     * 
{@code eventCount} must be greater than 0
     * 
Both of {@code commandBuffer}, and the elements of {@code pEvents} must have been created, allocated, or retrieved from the same {@code VkDevice}
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code commandBuffer} must be externally synchronized
     * 
Host access to the {@code VkCommandPool} that {@code commandBuffer} was allocated from must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
Primary Secondary
Both
Graphics Compute
     * 
     * 
See Also
     * 
     * 
{@link VkDependencyInfoKHR}
     *
     * @param commandBuffer    the command buffer into which the command is recorded.
     * @param pEvents          a pointer to an array of {@code eventCount} events to wait on.
     * @param pDependencyInfos a pointer to an array of {@code eventCount} {@link VkDependencyInfoKHR} structures, defining the second synchronization scope.
     */
    public static void vkCmdWaitEvents2KHR(VkCommandBuffer commandBuffer, @NativeType("VkEvent const *") LongBuffer pEvents, @NativeType("VkDependencyInfoKHR const *") VkDependencyInfoKHR.Buffer pDependencyInfos) {
        if (CHECKS) {
            check(pDependencyInfos, pEvents.remaining());
        }
        nvkCmdWaitEvents2KHR(commandBuffer, pEvents.remaining(), memAddress(pEvents), pDependencyInfos.address());
    }

    // --- [ vkCmdPipelineBarrier2KHR ] ---

    /** Unsafe version of: {@link #vkCmdPipelineBarrier2KHR CmdPipelineBarrier2KHR} */
    public static void nvkCmdPipelineBarrier2KHR(VkCommandBuffer commandBuffer, long pDependencyInfo) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdPipelineBarrier2KHR;
        if (CHECKS) {
            check(__functionAddress);
            VkDependencyInfoKHR.validate(pDependencyInfo);
        }
        callPPV(commandBuffer.address(), pDependencyInfo, __functionAddress);
    }

    /**
     * Insert a memory dependency.
     * 
     * 
C Specification
     * 
     * 
To record a pipeline barrier, call:
     * 
     * 

     * void vkCmdPipelineBarrier2KHR(
     *     VkCommandBuffer                             commandBuffer,
     *     const VkDependencyInfoKHR*                  pDependencyInfo);
     * 
     * 
Description
     * 
     * 
When {@link #vkCmdPipelineBarrier2KHR CmdPipelineBarrier2KHR} is submitted to a queue, it defines memory dependencies between commands that were submitted before it, and those submitted after it.
     * 
     * 
The first synchronization scope and access scope of each memory dependency defined by any element i of {@code pDependencyInfos} are applied to operations that occurred earlier in submission order.
     * 
     * 
The second synchronization scope and access scope of each memory dependency defined by any element i of {@code pDependencyInfos} are applied to operations that occurred later in submission order.
     * 
     * 
If {@code vkCmdPipelineBarrier2KHR} is recorded within a render pass instance, the synchronization scopes are limited to operations within the same subpass.
     * 
     * 
Valid Usage
     * 
     * 

     * 
If {@code vkCmdPipelineBarrier2KHR} is called within a render pass instance, the render pass must have been created with at least one {@link VkSubpassDependency} instance in {@link VkRenderPassCreateInfo}{@code ::pDependencies} that expresses a dependency from the current subpass to itself, with synchronization scopes and access scopes that are all supersets of the scopes defined in this command
     * 
If {@code vkCmdPipelineBarrier2KHR} is called within a render pass instance, it must not include any buffer memory barriers
     * 
If {@code vkCmdPipelineBarrier2KHR} is called within a render pass instance, the {@code image} member of any image memory barrier included in this command must be an attachment used in the current subpass both as an input attachment, and as either a color or depth/stencil attachment
     * 
If {@code vkCmdPipelineBarrier2KHR} is called within a render pass instance, the {@code oldLayout} and {@code newLayout} members of any image memory barrier included in this command must be equal
     * 
If {@code vkCmdPipelineBarrier2KHR} is called within a render pass instance, the {@code srcQueueFamilyIndex} and {@code dstQueueFamilyIndex} members of any image memory barrier included in this command must be equal
     * 
If {@code vkCmdPipelineBarrier2KHR} is called outside of a render pass instance, {@link VK11#VK_DEPENDENCY_VIEW_LOCAL_BIT DEPENDENCY_VIEW_LOCAL_BIT} must not be included in the dependency flags
     * 
If {@code vkCmdPipelineBarrier2KHR} is called within a render pass instance, the render pass must not have been started with {@link KHRDynamicRendering#vkCmdBeginRenderingKHR CmdBeginRenderingKHR}
     * 
The {@code synchronization2} feature must be enabled
     * 
The {@code srcStageMask} member of any element of the {@code pMemoryBarriers}, {@code pBufferMemoryBarriers}, or {@code pImageMemoryBarriers} members of {@code pDependencyInfo} must only include pipeline stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
The {@code dstStageMask} member of any element of the {@code pMemoryBarriers}, {@code pBufferMemoryBarriers}, or {@code pImageMemoryBarriers} members of {@code pDependencyInfo} must only include pipeline stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code commandBuffer} must be a valid {@code VkCommandBuffer} handle
     * 
{@code pDependencyInfo} must be a valid pointer to a valid {@link VkDependencyInfoKHR} structure
     * 
{@code commandBuffer} must be in the recording state
     * 
The {@code VkCommandPool} that {@code commandBuffer} was allocated from must support transfer, graphics, or compute operations
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code commandBuffer} must be externally synchronized
     * 
Host access to the {@code VkCommandPool} that {@code commandBuffer} was allocated from must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
Primary Secondary
Both
Transfer Graphics Compute
     * 
     * 
See Also
     * 
     * 
{@link VkDependencyInfoKHR}
     *
     * @param commandBuffer   the command buffer into which the command is recorded.
     * @param pDependencyInfo a pointer to a {@link VkDependencyInfoKHR} structure defining the scopes of this operation.
     */
    public static void vkCmdPipelineBarrier2KHR(VkCommandBuffer commandBuffer, @NativeType("VkDependencyInfoKHR const *") VkDependencyInfoKHR pDependencyInfo) {
        nvkCmdPipelineBarrier2KHR(commandBuffer, pDependencyInfo.address());
    }

    // --- [ vkCmdWriteTimestamp2KHR ] ---

    /**
     * Write a device timestamp into a query object.
     * 
     * 
C Specification
     * 
     * 
To request a timestamp, call:
     * 
     * 

     * void vkCmdWriteTimestamp2KHR(
     *     VkCommandBuffer                             commandBuffer,
     *     VkPipelineStageFlags2KHR                    stage,
     *     VkQueryPool                                 queryPool,
     *     uint32_t                                    query);
     * 
     * 
Description
     * 
     * 
When {@code vkCmdWriteTimestamp2KHR} is submitted to a queue, it defines an execution dependency on commands that were submitted before it, and writes a timestamp to a query pool.
     * 
     * 
The first synchronization scope includes all commands that occur earlier in submission order. The synchronization scope is limited to operations on the pipeline stage specified by {@code stage}.
     * 
     * 
The second synchronization scope includes only the timestamp write operation.
     * 
     * 
When the timestamp value is written, the availability status of the query is set to available.
     * 
     * 
Note
     * 
     * 
If an implementation is unable to detect completion and latch the timer at any specific stage of the pipeline, it may instead do so at any logically later stage.
     * 
     * 
     * 
Comparisons between timestamps are not meaningful if the timestamps are written by commands submitted to different queues.
     * 
     * 
Note
     * 
     * 
An example of such a comparison is subtracting an older timestamp from a newer one to determine the execution time of a sequence of commands.
     * 
     * 
     * 
If {@code vkCmdWriteTimestamp2KHR} is called while executing a render pass instance that has multiview enabled, the timestamp uses N consecutive query indices in the query pool (starting at {@code query}) where N is the number of bits set in the view mask of the subpass the command is executed in. The resulting query values are determined by an implementation-dependent choice of one of the following behaviors:
     * 
     * 

     * 
The first query is a timestamp value and (if more than one bit is set in the view mask) zero is written to the remaining queries. If two timestamps are written in the same subpass, the sum of the execution time of all views between those commands is the difference between the first query written by each command.
     * 
All N queries are timestamp values. If two timestamps are written in the same subpass, the sum of the execution time of all views between those commands is the sum of the difference between corresponding queries written by each command. The difference between corresponding queries may be the execution time of a single view.
     * 
     * 
     * 
In either case, the application can sum the differences between all N queries to determine the total execution time.
     * 
     * 
Valid Usage
     * 
     * 

     * 
If the geometry shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR}
     * 
If the tessellation shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR} or {@link #VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR}
     * 
If the conditional rendering feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT}
     * 
If the fragment density map feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT}
     * 
If the transform feedback feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT}
     * 
If the mesh shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}
     * 
If the task shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}
     * 
If the shading rate image feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV}
     * 
If the subpass shading feature is not enabled, {@code stage} must not contain {@link HUAWEISubpassShading#VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI}
     * 
If the invocation mask image feature is not enabled, {@code stage} must not contain {@link HUAWEIInvocationMask#VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI}
     * 
The {@code synchronization2} feature must be enabled
     * 
{@code stage} must only include a single pipeline stage
     * 
{@code stage} must only include stages valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
{@code queryPool} must have been created with a {@code queryType} of {@link VK10#VK_QUERY_TYPE_TIMESTAMP QUERY_TYPE_TIMESTAMP}
     * 
The query identified by {@code queryPool} and {@code query} must be unavailable
     * 
The command pool’s queue family must support a non-zero {@code timestampValidBits}
     * 
{@code query} must be less than the number of queries in {@code queryPool}
     * 
All queries used by the command must be unavailable
     * 
If {@code vkCmdWriteTimestamp2KHR} is called within a render pass instance, the sum of {@code query} and the number of bits set in the current subpass’s view mask must be less than or equal to the number of queries in {@code queryPool}
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code commandBuffer} must be a valid {@code VkCommandBuffer} handle
     * 
{@code stage} must be a valid combination of {@code VkPipelineStageFlagBits2KHR} values
     * 
{@code stage} must not be 0
     * 
{@code queryPool} must be a valid {@code VkQueryPool} handle
     * 
{@code commandBuffer} must be in the recording state
     * 
The {@code VkCommandPool} that {@code commandBuffer} was allocated from must support transfer, graphics, or compute operations
     * 
Both of {@code commandBuffer}, and {@code queryPool} must have been created, allocated, or retrieved from the same {@code VkDevice}
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code commandBuffer} must be externally synchronized
     * 
Host access to the {@code VkCommandPool} that {@code commandBuffer} was allocated from must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
Primary Secondary
Both
Transfer Graphics Compute
     *
     * @param commandBuffer the command buffer into which the command will be recorded.
     * @param stage         specifies a stage of the pipeline.
     * @param queryPool     the query pool that will manage the timestamp.
     * @param query         the query within the query pool that will contain the timestamp.
     */
    public static void vkCmdWriteTimestamp2KHR(VkCommandBuffer commandBuffer, @NativeType("VkPipelineStageFlags2KHR") long stage, @NativeType("VkQueryPool") long queryPool, @NativeType("uint32_t") int query) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdWriteTimestamp2KHR;
        if (CHECKS) {
            check(__functionAddress);
        }
        callPJJV(commandBuffer.address(), stage, queryPool, query, __functionAddress);
    }

    // --- [ vkQueueSubmit2KHR ] ---

    /**
     * Unsafe version of: {@link #vkQueueSubmit2KHR QueueSubmit2KHR}
     *
     * @param submitCount the number of elements in the {@code pSubmits} array.
     */
    public static int nvkQueueSubmit2KHR(VkQueue queue, int submitCount, long pSubmits, long fence) {
        long __functionAddress = queue.getCapabilities().vkQueueSubmit2KHR;
        if (CHECKS) {
            check(__functionAddress);
            if (pSubmits != NULL) { Struct.validate(pSubmits, submitCount, VkSubmitInfo2KHR.SIZEOF, VkSubmitInfo2KHR::validate); }
        }
        return callPPJI(queue.address(), submitCount, pSubmits, fence, __functionAddress);
    }

    /**
     * Submits command buffers to a queue.
     * 
     * 
C Specification
     * 
     * 
To submit command buffers to a queue, call:
     * 
     * 

     * VkResult vkQueueSubmit2KHR(
     *     VkQueue                                     queue,
     *     uint32_t                                    submitCount,
     *     const VkSubmitInfo2KHR*                     pSubmits,
     *     VkFence                                     fence);
     * 
     * 
Description
     * 
     * 
{@code vkQueueSubmit2KHR} is a queue submission command, with each batch defined by an element of {@code pSubmits}.
     * 
     * 
Semaphore operations submitted with {@link #vkQueueSubmit2KHR QueueSubmit2KHR} have additional ordering constraints compared to other submission commands, with dependencies involving previous and subsequent queue operations. Information about these additional constraints can be found in the semaphore section of the synchronization chapter.
     * 
     * 
If any command buffer submitted to this queue is in the executable state, it is moved to the pending state. Once execution of all submissions of a command buffer complete, it moves from the pending state, back to the executable state. If a command buffer was recorded with the {@link VK10#VK_COMMAND_BUFFER_USAGE_ONE_TIME_SUBMIT_BIT COMMAND_BUFFER_USAGE_ONE_TIME_SUBMIT_BIT} flag, it instead moves back to the invalid state.
     * 
     * 
If {@code vkQueueSubmit2KHR} fails, it may return {@link VK10#VK_ERROR_OUT_OF_HOST_MEMORY ERROR_OUT_OF_HOST_MEMORY} or {@link VK10#VK_ERROR_OUT_OF_DEVICE_MEMORY ERROR_OUT_OF_DEVICE_MEMORY}. If it does, the implementation must ensure that the state and contents of any resources or synchronization primitives referenced by the submitted command buffers and any semaphores referenced by {@code pSubmits} is unaffected by the call or its failure. If {@code vkQueueSubmit2KHR} fails in such a way that the implementation is unable to make that guarantee, the implementation must return {@link VK10#VK_ERROR_DEVICE_LOST ERROR_DEVICE_LOST}. See Lost Device.
     * 
     * 
Valid Usage
     * 
     * 

     * 
If {@code fence} is not {@link VK10#VK_NULL_HANDLE NULL_HANDLE}, {@code fence} must be unsignaled
     * 
If {@code fence} is not {@link VK10#VK_NULL_HANDLE NULL_HANDLE}, {@code fence} must not be associated with any other queue command that has not yet completed execution on that queue
     * 
The {@code synchronization2} feature must be enabled
     * 
If a command recorded into the {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} referenced an {@code VkEvent}, that event must not be referenced by a command that has been submitted to another queue and is still in the pending state
     * 
The {@code semaphore} member of any binary semaphore element of the {@code pSignalSemaphoreInfos} member of any element of {@code pSubmits} must be unsignaled when the semaphore signal operation it defines is executed on the device
     * 
The {@code stageMask} member of any element of the {@code pSignalSemaphoreInfos} member of any element of {@code pSubmits} must only include pipeline stages that are supported by the queue family which {@code queue} belongs to
     * 
The {@code stageMask} member of any element of the {@code pWaitSemaphoreInfos} member of any element of {@code pSubmits} must only include pipeline stages that are supported by the queue family which {@code queue} belongs to
     * 
When a semaphore wait operation for a binary semaphore is executed, as defined by the {@code semaphore} member of any element of the {@code pWaitSemaphoreInfos} member of any element of {@code pSubmits}, there must be no other queues waiting on the same semaphore
     * 
The {@code semaphore} member of any element of the {@code pWaitSemaphoreInfos} member of any element of {@code pSubmits} must be semaphores that are signaled, or have semaphore signal operations previously submitted for execution
     * 
Any {@code semaphore} member of any element of the {@code pWaitSemaphoreInfos} member of any element of {@code pSubmits} that was created with a {@code VkSemaphoreTypeKHR} of {@link KHRTimelineSemaphore#VK_SEMAPHORE_TYPE_BINARY_KHR SEMAPHORE_TYPE_BINARY_KHR} must reference a semaphore signal operation that has been submitted for execution and any semaphore signal operations on which it depends (if any) must have also been submitted for execution
     * 
The {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} must be in the pending or executable state
     * 
If a command recorded into the {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} was not recorded with the {@link VK10#VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT}, it must not be in the pending state
     * 
Any secondary command buffers recorded into the {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} must be in the pending or executable state
     * 
If any secondary command buffers recorded into the {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} was not recorded with the {@link VK10#VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT}, it must not be in the pending state
     * 
The {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} must have been allocated from a {@code VkCommandPool} that was created for the same queue family {@code queue} belongs to
     * 
If a command recorded into the {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} includes a Queue Family Transfer Acquire Operation, there must exist a previously submitted Queue Family Transfer Release Operation on a queue in the queue family identified by the acquire operation, with parameters matching the acquire operation as defined in the definition of such acquire operations, and which happens before the acquire operation
     * 
If a command recorded into the {@code commandBuffer} member of any element of the {@code pCommandBufferInfos} member of any element of {@code pSubmits} was a {@link VK10#vkCmdBeginQuery CmdBeginQuery} whose {@code queryPool} was created with a {@code queryType} of {@link KHRPerformanceQuery#VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR QUERY_TYPE_PERFORMANCE_QUERY_KHR}, the profiling lock must have been held continuously on the {@code VkDevice} that {@code queue} was retrieved from, throughout recording of those command buffers
     * 
If {@code queue} was not created with {@link VK11#VK_DEVICE_QUEUE_CREATE_PROTECTED_BIT DEVICE_QUEUE_CREATE_PROTECTED_BIT}, the {@code flags} member of any element of {@code pSubmits} must not include {@link #VK_SUBMIT_PROTECTED_BIT_KHR SUBMIT_PROTECTED_BIT_KHR}
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code queue} must be a valid {@code VkQueue} handle
     * 
If {@code submitCount} is not 0, {@code pSubmits} must be a valid pointer to an array of {@code submitCount} valid {@link VkSubmitInfo2KHR} structures
     * 
If {@code fence} is not {@link VK10#VK_NULL_HANDLE NULL_HANDLE}, {@code fence} must be a valid {@code VkFence} handle
     * 
Both of {@code fence}, and {@code queue} that are valid handles of non-ignored parameters must have been created, allocated, or retrieved from the same {@code VkDevice}
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code queue} must be externally synchronized
     * 
Host access to {@code fence} must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
-
-
Any
     * 
     * 
Return Codes
     * 
     * 

     * 
On success, this command returns
     * 

     * 
{@link VK10#VK_SUCCESS SUCCESS}
     * 
     * 
On failure, this command returns
     * 

     * 
{@link VK10#VK_ERROR_OUT_OF_HOST_MEMORY ERROR_OUT_OF_HOST_MEMORY}
     * 
{@link VK10#VK_ERROR_OUT_OF_DEVICE_MEMORY ERROR_OUT_OF_DEVICE_MEMORY}
     * 
{@link VK10#VK_ERROR_DEVICE_LOST ERROR_DEVICE_LOST}
     * 
     * 
     * 
     * 
See Also
     * 
     * 
{@link VkSubmitInfo2KHR}
     *
     * @param queue    the queue that the command buffers will be submitted to.
     * @param pSubmits a pointer to an array of {@link VkSubmitInfo2KHR} structures, each specifying a command buffer submission batch.
     * @param fence    an optional handle to a fence to be signaled once all submitted command buffers have completed execution. If {@code fence} is not {@link VK10#VK_NULL_HANDLE NULL_HANDLE}, it defines a fence signal operation.
     */
    @NativeType("VkResult")
    public static int vkQueueSubmit2KHR(VkQueue queue, @Nullable @NativeType("VkSubmitInfo2KHR const *") VkSubmitInfo2KHR.Buffer pSubmits, @NativeType("VkFence") long fence) {
        return nvkQueueSubmit2KHR(queue, remainingSafe(pSubmits), memAddressSafe(pSubmits), fence);
    }

    // --- [ vkCmdWriteBufferMarker2AMD ] ---

    /**
     * Execute a pipelined write of a marker value into a buffer.
     * 
     * 
C Specification
     * 
     * 
To write a 32-bit marker value into a buffer as a pipelined operation, call:
     * 
     * 

     * void vkCmdWriteBufferMarker2AMD(
     *     VkCommandBuffer                             commandBuffer,
     *     VkPipelineStageFlags2KHR                    stage,
     *     VkBuffer                                    dstBuffer,
     *     VkDeviceSize                                dstOffset,
     *     uint32_t                                    marker);
     * 
     * 
Description
     * 
     * 
The command will write the 32-bit marker value into the buffer only after all preceding commands have finished executing up to at least the specified pipeline stage. This includes the completion of other preceding {@code vkCmdWriteBufferMarker2AMD} commands so long as their specified pipeline stages occur either at the same time or earlier than this command’s specified {@code stage}.
     * 
     * 
While consecutive buffer marker writes with the same {@code stage} parameter implicitly complete in submission order, memory and execution dependencies between buffer marker writes and other operations must still be explicitly ordered using synchronization commands. The access scope for buffer marker writes falls under the {@link VK10#VK_ACCESS_TRANSFER_WRITE_BIT ACCESS_TRANSFER_WRITE_BIT}, and the pipeline stages for identifying the synchronization scope must include both {@code stage} and {@link VK10#VK_PIPELINE_STAGE_TRANSFER_BIT PIPELINE_STAGE_TRANSFER_BIT}.
     * 
     * 
Note
     * 
     * 
Similar to {@code vkCmdWriteTimestamp2KHR}, if an implementation is unable to write a marker at any specific pipeline stage, it may instead do so at any logically later stage.
     * 
     * 
     * 
Note
     * 
     * 
Implementations may only support a limited number of pipelined marker write operations in flight at a given time. Thus an excessive number of marker write operations may degrade command execution performance.
     * 
     * 
     * 
Valid Usage
     * 
     * 

     * 
If the geometry shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR}
     * 
If the tessellation shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR} or {@link #VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR}
     * 
If the conditional rendering feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT}
     * 
If the fragment density map feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT}
     * 
If the transform feedback feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT}
     * 
If the mesh shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV PIPELINE_STAGE_2_MESH_SHADER_BIT_NV}
     * 
If the task shaders feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV PIPELINE_STAGE_2_TASK_SHADER_BIT_NV}
     * 
If the shading rate image feature is not enabled, {@code stage} must not contain {@link #VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV}
     * 
If the subpass shading feature is not enabled, {@code stage} must not contain {@link HUAWEISubpassShading#VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI}
     * 
If the invocation mask image feature is not enabled, {@code stage} must not contain {@link HUAWEIInvocationMask#VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI}
     * 
The {@code synchronization2} feature must be enabled
     * 
{@code stage} must include only a single pipeline stage
     * 
{@code stage} must include only stages that are valid for the queue family that was used to create the command pool that {@code commandBuffer} was allocated from
     * 
{@code dstOffset} must be less than or equal to the size of {@code dstBuffer} minus 4
     * 
{@code dstBuffer} must have been created with the {@link VK10#VK_BUFFER_USAGE_TRANSFER_DST_BIT BUFFER_USAGE_TRANSFER_DST_BIT} usage flag
     * 
If {@code dstBuffer} is non-sparse then it must be bound completely and contiguously to a single {@code VkDeviceMemory} object
     * 
{@code dstOffset} must be a multiple of 4
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code commandBuffer} must be a valid {@code VkCommandBuffer} handle
     * 
{@code stage} must be a valid combination of {@code VkPipelineStageFlagBits2KHR} values
     * 
{@code stage} must not be 0
     * 
{@code dstBuffer} must be a valid {@code VkBuffer} handle
     * 
{@code commandBuffer} must be in the recording state
     * 
The {@code VkCommandPool} that {@code commandBuffer} was allocated from must support transfer, graphics, or compute operations
     * 
Both of {@code commandBuffer}, and {@code dstBuffer} must have been created, allocated, or retrieved from the same {@code VkDevice}
     * 
     * 
     * 
Host Synchronization
     * 
     * 

     * 
Host access to {@code commandBuffer} must be externally synchronized
     * 
Host access to the {@code VkCommandPool} that {@code commandBuffer} was allocated from must be externally synchronized
     * 
     * 
     * 
Command Properties
     * 
     * 
     * 
     * 
     * 
Command Buffer Levels
Render Pass Scope
Supported Queue Types
Primary Secondary
Both
Transfer Graphics Compute
     *
     * @param commandBuffer the command buffer into which the command will be recorded.
     * @param stage         specifies the pipeline stage whose completion triggers the marker write.
     * @param dstBuffer     the buffer where the marker will be written.
     * @param dstOffset     the byte offset into the buffer where the marker will be written.
     * @param marker        the 32-bit value of the marker.
     */
    public static void vkCmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, @NativeType("VkPipelineStageFlags2KHR") long stage, @NativeType("VkBuffer") long dstBuffer, @NativeType("VkDeviceSize") long dstOffset, @NativeType("uint32_t") int marker) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdWriteBufferMarker2AMD;
        if (CHECKS) {
            check(__functionAddress);
        }
        callPJJJV(commandBuffer.address(), stage, dstBuffer, dstOffset, marker, __functionAddress);
    }

    // --- [ vkGetQueueCheckpointData2NV ] ---

    /**
     * Unsafe version of: {@link #vkGetQueueCheckpointData2NV GetQueueCheckpointData2NV}
     *
     * @param pCheckpointDataCount a pointer to an integer related to the number of checkpoint markers available or queried, as described below.
     */
    public static void nvkGetQueueCheckpointData2NV(VkQueue queue, long pCheckpointDataCount, long pCheckpointData) {
        long __functionAddress = queue.getCapabilities().vkGetQueueCheckpointData2NV;
        if (CHECKS) {
            check(__functionAddress);
        }
        callPPPV(queue.address(), pCheckpointDataCount, pCheckpointData, __functionAddress);
    }

    /**
     * Retrieve diagnostic checkpoint data.
     * 
     * 
C Specification
     * 
     * 
If the device encounters an error during execution, the implementation will return a {@link VK10#VK_ERROR_DEVICE_LOST ERROR_DEVICE_LOST} error to the application at some point during host execution. When this happens, the application can call {@link #vkGetQueueCheckpointData2NV GetQueueCheckpointData2NV} to retrieve information on the most recent diagnostic checkpoints that were executed by the device.
     * 
     * 

     * void vkGetQueueCheckpointData2NV(
     *     VkQueue                                     queue,
     *     uint32_t*                                   pCheckpointDataCount,
     *     VkCheckpointData2NV*                        pCheckpointData);
     * 
     * 
Description
     * 
     * 
If {@code pCheckpointData} is {@code NULL}, then the number of checkpoint markers available is returned in {@code pCheckpointDataCount}. Otherwise, {@code pCheckpointDataCount} must point to a variable set by the user to the number of elements in the {@code pCheckpointData} array, and on return the variable is overwritten with the number of structures actually written to {@code pCheckpointData}.
     * 
     * 
If {@code pCheckpointDataCount} is less than the number of checkpoint markers available, at most {@code pCheckpointDataCount} structures will be written.
     * 
     * 
Valid Usage
     * 
     * 

     * 
The device that {@code queue} belongs to must be in the lost state
     * 
     * 
     * 
Valid Usage (Implicit)
     * 
     * 

     * 
{@code queue} must be a valid {@code VkQueue} handle
     * 
{@code pCheckpointDataCount} must be a valid pointer to a {@code uint32_t} value
     * 
If the value referenced by {@code pCheckpointDataCount} is not 0, and {@code pCheckpointData} is not {@code NULL}, {@code pCheckpointData} must be a valid pointer to an array of {@code pCheckpointDataCount} {@link VkCheckpointData2NV} structures
     * 
     * 
     * 
See Also
     * 
     * 
{@link VkCheckpointData2NV}
     *
     * @param queue                the {@code VkQueue} object the caller would like to retrieve checkpoint data for
     * @param pCheckpointDataCount a pointer to an integer related to the number of checkpoint markers available or queried, as described below.
     * @param pCheckpointData      either {@code NULL} or a pointer to an array of {@link VkCheckpointData2NV} structures.
     */
    public static void vkGetQueueCheckpointData2NV(VkQueue queue, @NativeType("uint32_t *") IntBuffer pCheckpointDataCount, @Nullable @NativeType("VkCheckpointData2NV *") VkCheckpointData2NV.Buffer pCheckpointData) {
        if (CHECKS) {
            check(pCheckpointDataCount, 1);
            checkSafe(pCheckpointData, pCheckpointDataCount.get(pCheckpointDataCount.position()));
        }
        nvkGetQueueCheckpointData2NV(queue, memAddress(pCheckpointDataCount), memAddressSafe(pCheckpointData));
    }

    /** Array version of: {@link #vkCmdWaitEvents2KHR CmdWaitEvents2KHR} */
    public static void vkCmdWaitEvents2KHR(VkCommandBuffer commandBuffer, @NativeType("VkEvent const *") long[] pEvents, @NativeType("VkDependencyInfoKHR const *") VkDependencyInfoKHR.Buffer pDependencyInfos) {
        long __functionAddress = commandBuffer.getCapabilities().vkCmdWaitEvents2KHR;
        if (CHECKS) {
            check(__functionAddress);
            check(pDependencyInfos, pEvents.length);
            Struct.validate(pDependencyInfos.address(), pEvents.length, VkDependencyInfoKHR.SIZEOF, VkDependencyInfoKHR::validate);
        }
        callPPPV(commandBuffer.address(), pEvents.length, pEvents, pDependencyInfos.address(), __functionAddress);
    }

    /** Array version of: {@link #vkGetQueueCheckpointData2NV GetQueueCheckpointData2NV} */
    public static void vkGetQueueCheckpointData2NV(VkQueue queue, @NativeType("uint32_t *") int[] pCheckpointDataCount, @Nullable @NativeType("VkCheckpointData2NV *") VkCheckpointData2NV.Buffer pCheckpointData) {
        long __functionAddress = queue.getCapabilities().vkGetQueueCheckpointData2NV;
        if (CHECKS) {
            check(__functionAddress);
            check(pCheckpointDataCount, 1);
            checkSafe(pCheckpointData, pCheckpointDataCount[0]);
        }
        callPPPV(queue.address(), pCheckpointDataCount, memAddressSafe(pCheckpointData), __functionAddress);
    }

}