selverify.chiselverify.0.4.0.source-code.accualu_converted.v Maven / Gradle / Ivy

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/* Generated by Yosys 0.9+2406 (git sha1 072b14f1, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os) */

module accualu(clock, reset, op, din, ena, accu);
  wire [31:0] _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire [31:0] _05_;
  wire [31:0] _06_;
  wire _07_;
  wire [31:0] _08_;
  wire _09_;
  wire [31:0] _10_;
  wire _11_;
  wire [31:0] _12_;
  wire _13_;
  wire [31:0] _14_;
  output [31:0] accu;
  reg [31:0] accureg;
  input clock;
  input [31:0] din;
  input ena;
  input [2:0] op;
  wire [31:0] res;
  input reset;
  assign _11_ = op == 3'h3;
  assign _12_ = accureg | din;
  assign _13_ = op == 3'h4;
  assign _14_ = accureg ^ din;
  assign _01_ = op == 3'h5;
  assign _02_ = op == 3'h6;
  assign _03_ = op == 3'h7;
  assign _04_ = op == 3'h0;
  function [31:0] \28 ;
    input [31:0] a;
    input [255:0] b;
    input [7:0] s;
    (* parallel_case *)
    casez (s)
      8'b???????1:
        \28  = b[31:0];
      8'b??????1?:
        \28  = b[63:32];
      8'b?????1??:
        \28  = b[95:64];
      8'b????1???:
        \28  = b[127:96];
      8'b???1????:
        \28  = b[159:128];
      8'b??1?????:
        \28  = b[191:160];
      8'b?1??????:
        \28  = b[223:192];
      8'b1???????:
        \28  = b[255:224];
      default:
        \28  = a;
    endcase
  endfunction
  assign res = \28 (accureg, { accureg, 1'h0, accureg[31:1], din, _14_, _12_, _10_, _08_, _00_ }, { _04_, _03_, _02_, _01_, _13_, _11_, _09_, _07_ });
  assign _00_ = accureg + din;
  assign _05_ = ena ? res : accureg;
  assign _06_ = reset ? 32'd0 : _05_;
  always @(posedge clock)
      accureg <= _06_;
  assign _07_ = op == 3'h1;
  assign _08_ = accureg - din;
  assign _09_ = op == 3'h2;
  assign _10_ = accureg & din;
  assign accu = accureg;
endmodule