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boarddefs.xunlong_orangepi-zero-plus.txt Maven / Gradle / Ivy
# https://linux-sunxi.org/Xunlong_Orange_Pi_Zero_Plus
General, DEFAULT, 1, 3v3
General, DEFAULT, 2, 5v
General, DEFAULT, 4, 5v
General, DEFAULT, 6, GND
General, DEFAULT, 9, GND
General, DEFAULT, 14, GND
General, DEFAULT, 17, 3v3
General, DEFAULT, 20, GND
General, DEFAULT, 25, GND
# GPIO, Header, GPIO#, Name, Physical Pin, Modes, Chip, Line
GPIO, DEFAULT, 12, SDA.0, 3, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 12 # TWI0_SDA / PA12 / GPIO12 **
GPIO, DEFAULT, 11, SCL.0, 5, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 11 # TWI0_SCK / PA11 / GPIO11 **
GPIO, DEFAULT, 6, PA06, 7, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 6 # PWM1 / PA06 / GPIO6
GPIO, DEFAULT, 198, TXD.1, 8, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 198 # UART1_TX / PG06 / GPIO198
GPIO, DEFAULT, 199, RXD.1, 10, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 199 # UART1_RX / PG07 / GPIO199
GPIO, DEFAULT, 1, RXD.2, 11, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 1 # UART2_RX / PA01 / GPIO1
GPIO, DEFAULT, 7, PA07, 12, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 7 # SIM_CLK / PA_EINT7 / PA07 / GPIO7
GPIO, DEFAULT, 0, TXD.2, 13, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 0 # UART2_TX / PA00 / GPIO0
GPIO, DEFAULT, 3, CTS.2, 15, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 3 # UART2_CTS / PA03 / GPIO3
GPIO, DEFAULT, 19, SDA.1, 16, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 19 # TWI1-SDA / PA19 / GPIO19
GPIO, DEFAULT, 18, SCL.1, 18, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 18 # TWI1-SCK / PA18 / GPIO18
GPIO, DEFAULT, 15, MOSI.1, 19, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 15 # SPI1_MOSI / PA15 / GPIO15
GPIO, DEFAULT, 16, MISO.1, 21, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 16 # SPI1_MISO / PA16 / GPIO16
GPIO, DEFAULT, 2, RTS.2, 22, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 2 # UART2_RTS / PA02 / GPIO2
GPIO, DEFAULT, 14, SCLK.1, 23, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 14 # SPI1_CLK / PA14 / GPIO14
GPIO, DEFAULT, 13, CE.1, 24, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 13 # SPI1_CS / PA13 / GPIO13
GPIO, DEFAULT, 10, PA10, 26, DIGITAL_INPUT | DIGITAL_OUTPUT, 1, 10 # SIM_DET / PA_EINT10 / PA10 / GPIO10
