spinal.lib.misc.plic.WishbonePlic.scala Maven / Gradle / Ivy
package spinal.lib.misc.plic
import spinal.core._
import spinal.lib._
import spinal.lib.bus.wishbone._
//Interrupt 0 can't be used
class WishbonePlic(sourceCount : Int, targetCount : Int) extends Component{
val priorityWidth = 2
val plicMapping = PlicMapping.sifive
import plicMapping._
val io = new Bundle {
val bus = slave(Wishbone(WishboneConfig(22-2, 32)))
val sources = in Bits (sourceCount bits)
val targets = out Bits (targetCount bits)
}
val gateways = (for ((source, id) <- (io.sources.asBools, 1 until sourceCount).zipped) yield PlicGatewayActiveHigh(
source = source,
id = id,
priorityWidth = priorityWidth
)).toSeq
val targets = for (i <- 0 until targetCount) yield PlicTarget(
gateways = gateways,
priorityWidth = priorityWidth
)
io.targets := targets.map(_.iep).asBits
val bus = WishboneSlaveFactory(io.bus)
val mapping = PlicMapper(bus, plicMapping)(
gateways = gateways,
targets = targets
)
}