spinal.lib.bus.regif.Factory.IntrS1.scala Maven / Gradle / Ivy

Go to download
package spinal.lib.bus.regif

import spinal.core._

import scala.collection.mutable.ListBuffer

/* S1(STATUS) 1 Interrupt Register Group used for 2nd interrupt signal merge
  * 1. STATUS: status register, status = raw && (!mask)
  * ```verilog demo
  * always @(*) begin
  *   case(addr) begin
  *     `xxx_STATUS: bus_rdata = {28'b0, signal_3....signal_0};
  *     ....
  *   endcase
  * end
  * assign  xxx_int = status_3 || status_2 || status_1 || status_0 ;
  * ```
  */
class IntrS1(val name: String, offset: BigInt, doc: String, bi: BusIf, sec: Secure, grp: GrpTag) extends RegSliceGrp(offset, maxSize = 1*bi.bw, doc, sec, grp)(bi) with IntrBase {
  val STATUS = this.newRegAt(0, s"${doc} MS2-status Register\n status = raw && (!mask)")(SymbolName(s"${name}_INT_STATUS"))

  @deprecated("IntrS1 without mask, sou maskRstVal is invalid, use fieldAt(pos: Int, signal: T, doc: String) instead", "???")
  def fieldAt[T <: BaseType](pos: Int, signal: T, maskRstVal: BigInt, doc: String)(implicit symbol: SymbolName): T = fieldAt(pos, signal, doc)(symbol)
  def fieldAt[T <: BaseType](pos: Int, signal: T, doc: String)(implicit symbol: SymbolName): T = {
    val nm = if (symbol.name.startsWith("