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com.sun.electric.lib.orangeGeneric180.jelib Maven / Gradle / Ivy
# header information:
HorangeGeneric180|8.09a|USER_electrical_units()I70464
# Views:
Vicon|ic
Vschematic|sch
# Tools:
# Technologies:
# Cell NMOS4f;1{ic}
CNMOS4f;1{ic}||artwork|1021415734000|1046880615000|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5G1;HNPX3.25;Y-0.25;)I2|ATTR_W(D6G1;HNPX1.75;Y0.75;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y-2.5;)I0|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NPin|pin@0||-0.25|-0.75||||
NPin|pin@1||-0.25|-0.25||||
NPin|pin@2||-0.75|-0.5|1|1|RR|
NPin|pin@3||0|-0.5|||RR|
Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
Ngeneric:Invisible-Pin|pin@5||0|-2||||
NPin|pin@6||-1.5|0|1|1|RR|
NPin|pin@7||-3|0|||RR|
Nschematic:Bus_Pin|pin@8||-3|0|-2|-2||
Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
NPin|pin@10||0|-2||||
NPin|pin@11||-1.5|1|1|1||
NPin|pin@12||-1.5|-1|1|1||
NPin|pin@13||0|-1||||
NPin|pin@14||-0.75|-1|1|1||
NPin|pin@15||-0.75|1|1|1||
NPin|pin@16||0|1||||
NPin|pin@17||0|2||||
AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
AThicker|net@4|||FS1800|pin@7||-3|0|pin@6||-1.5|0|ART_color()I74
AThicker|net@5|||FS900|pin@11||-1.5|1|pin@12||-1.5|-1|ART_color()I74
AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
Eb||D5G1;|pin@4||B
Ed||D5G1;|pin@9||B
Eg||D5G1;|pin@8||I
Es||D5G1;|pin@5||B
X
# Cell NMOS4f;1{sch}
CNMOS4f;1{sch}||schematic|1021415734000|1255227100254||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5G1;HNPX-18;Y-11.5;)I2|ATTR_W(D5G1;HNPX-18;Y-10.5;)I3|ATTR_drain_shared(D5G1;HNPX-18.5;Y-13.75;)I0|ATTR_source_shared(D5G1;HNPX-18.5;Y-14.75;)I0|ATTR_SPICE_template(D5G1;NTX-2.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOS4f;1{ic}|NMOS4f@0||23.5|3.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||4.5|-7.5||||
NOff-Page|conn@1||4.5|-12.5||||
NOff-Page|conn@2||4.5|0||||
NOff-Page|conn@3||-18.5|-6.5||||
N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
Ngeneric:Invisible-Pin|pin@0||-2|6.5|||||ART_message(D5G3;)S[4 terminal device]
NWire_Pin|pin@1||0|-12.5||||
NWire_Pin|pin@2||0|0||||
Ngeneric:Invisible-Pin|pin@3||-1.5|11|||||ART_message(D5G6;)S[NMOS4f]
Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
Eb||D5G2;|conn@0|y|B
Ed||D5G2;|conn@2|y|B
Eg||D5G2;|conn@3|a|I
Es||D5G2;|conn@1|y|B
X
# Cell NMOS4fwk;1{ic}
CNMOS4fwk;1{ic}||artwork|1021415734000|1098403749000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y-2.5;)I0|prototype_center()I[0,-8000]
Ngeneric:Facet-Center|art@0||0|0||||AV
NPin|pin@0||0|2||||
NPin|pin@1||0|0.75||||
NPin|pin@2||-0.75|0.75|1|1||
NPin|pin@3||-0.75|-0.75|1|1||
NPin|pin@4||0|-0.75||||
NPin|pin@5||-1.25|-0.75|1|1||
NPin|pin@6||-1.25|0.75|1|1||
NPin|pin@7||0|-2||||
Nschematic:Bus_Pin|pin@8||0|2|-2|-2||
Nschematic:Bus_Pin|pin@9||-3|0|-2|-2||
NPin|pin@10||-3|0|||RR|
NPin|pin@11||-1.25|0|1|1|RR|
Ngeneric:Invisible-Pin|pin@12||0|-2||||
Ngeneric:Invisible-Pin|pin@13||-0.5|0|||||ART_message(D5G1;)S[wk]
NPin|pin@14||0|-0.5||||
NPin|pin@15||-0.75|-0.5|1|1||
NPin|pin@16||-0.5|-0.75|1|1|YRR|
NPin|pin@17||-0.75|-0.5|1|1|Y|
NPin|pin@18||-0.75|-0.5|1|1||
NPin|pin@19||-0.5|-0.25|1|1|RR|
Nschematic:Bus_Pin|pin@20||0|-0.5|-2|-2||
AThicker|net@0|||FS900|pin@0||0|2|pin@1||0|0.75|ART_color()I74
AThicker|net@1|||FS0|pin@1||0|0.75|pin@2||-0.75|0.75|ART_color()I74
AThicker|net@2|||FS1800|pin@3||-0.75|-0.75|pin@4||0|-0.75|ART_color()I74
AThicker|net@3|||FS900|pin@4||0|-0.75|pin@7||0|-2|ART_color()I74
AThicker|net@4|||FS900|pin@6||-1.25|0.75|pin@5||-1.25|-0.75|ART_color()I74
AThicker|net@5|||FS1800|pin@10||-3|0|pin@11||-1.25|0|ART_color()I74
AThicker|net@6|||FS900|pin@2||-0.75|0.75|pin@3||-0.75|-0.75|ART_color()I74
AThicker|net@7|||FS1800|pin@15||-0.75|-0.5|pin@14||0|-0.5|ART_color()I74
AThicker|net@8|||FS3150|pin@16||-0.5|-0.75|pin@17||-0.75|-0.5|ART_color()I74
AThicker|net@9|||FS450|pin@19||-0.5|-0.25|pin@18||-0.75|-0.5|ART_color()I74
Eb||D5G1;|pin@20||B
Ed||D5G1;|pin@8||B
Eg||D5G1;|pin@9||I
Es||D5G1;|pin@12||B
X
# Cell NMOS4fwk;1{sch}
CNMOS4fwk;1{sch}||schematic|1021415734000|1047947164000||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNPX-9;Y-13.5;)I2|ATTR_W(D5G1;HNPX-8.5;Y-12.5;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-16.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-17.75;)I0|ATTR_SPICE_template(D5G1;NTX0.5;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOS4fwk;1{ic}|NMOS4fwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_M(T)I1
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-10|-8||||
NOff-Page|conn@1||4.5|0||||
NOff-Page|conn@2||6|-16.5||||
NOff-Page|conn@3||6|-9|||YRR|
N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
Ngeneric:Invisible-Pin|pin@0||0|8.5|||||ART_message(D5G6;)S[NMOS4fwk]
NWire_Pin|pin@1||0|0||||
NWire_Pin|pin@2||0|-16.5||||
Awire|net@0|||900|pin@1||0|0|nmos4p@0|d|0|-6
Awire|net@1|||1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
Awire|net@3|||1800|pin@2||0|-16.5|conn@2|a|4|-16.5
Awire|net@4|||900|nmos4p@0|s|0|-10|pin@2||0|-16.5
Awire|net@5|||1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
Eb||D5G2;|conn@3|y|B
Ed||D5G2;|conn@1|y|B
Eg||D5G2;|conn@0|a|I
Es||D5G2;|conn@2|y|B
X
# Cell NMOSf;1{ic}
CNMOSf;1{ic}||artwork|1021415734000|1046884569000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y-2.5;)I0|prototype_center()I[0,-8000]
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@0||0|-2||||
NPin|pin@1||-1.5|0|1|1|RR|
NPin|pin@2||-3|0|||RR|
Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
NPin|pin@5||0|-2||||
NPin|pin@6||-1.5|1|1|1||
NPin|pin@7||-1.5|-1|1|1||
NPin|pin@8||0|-1||||
NPin|pin@9||-0.75|-1|1|1||
NPin|pin@10||-0.75|1|1|1||
NPin|pin@11||0|1||||
NPin|pin@12||0|2||||
AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I74
AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I74
AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
Ed||D5G1;|pin@4||B
Eg||D5G1;|pin@3||I
Es||D5G1;|pin@0||B
X
# Cell NMOSf;1{sch}
CNMOSf;1{sch}||schematic|1021415734000|1098393023000||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNPX-9;Y-13.5;)I2|ATTR_W(D5G1;HNPX-8.5;Y-12.5;)I3|ATTR_drain_shared(D5G1;HNPX-9;Y-16.5;)I0|ATTR_source_shared(D5G1;HNPX-9;Y-18;)I0|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOSf;1{ic}|NMOSf@0||26.5|8.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||6|-16.5||||
NOff-Page|conn@1||6.5|0||||
NOff-Page|conn@2||-16.5|-8||||
NGround|gnd@0||5|-11||||
N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
NWire_Pin|pin@0||0|-16.5||||
NWire_Pin|pin@1||0|0||||
Ngeneric:Invisible-Pin|pin@2||-6.5|11|||||ART_message(D5G6;)S[NMOSf]
Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
Ed||D5G2;|conn@1|y|B
Eg||D5G2;|conn@2|a|I
Es||D5G2;|conn@0|y|B
X
# Cell NMOSfwk;1{ic}
CNMOSfwk;1{ic}||artwork|1021415734000|1047945058000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y-2.5;)I0|prototype_center()I[0,-8000]
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
Ngeneric:Invisible-Pin|pin@1||0|-2||||
NPin|pin@2||-1.25|0|1|1|RR|
NPin|pin@3||-3|0|||RR|
Nschematic:Bus_Pin|pin@4||-3|0|-2|-2||
Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
NPin|pin@6||0|-2||||
NPin|pin@7||-1.25|0.75|1|1||
NPin|pin@8||-1.25|-0.75|1|1||
NPin|pin@9||0|-0.75||||
NPin|pin@10||-0.75|-0.75|1|1||
NPin|pin@11||-0.75|0.75|1|1||
NPin|pin@12||0|0.75||||
NPin|pin@13||0|2||||
AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I74
AThicker|net@1|||FS1800|pin@3||-3|0|pin@2||-1.25|0|ART_color()I74
AThicker|net@2|||FS900|pin@7||-1.25|0.75|pin@8||-1.25|-0.75|ART_color()I74
AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I74
AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I74
AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I74
AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I74
Ed||D5G1;|pin@5||B
Eg||D5G1;|pin@4||I
Es||D5G1;|pin@1||B
X
# Cell NMOSfwk;1{sch}
CNMOSfwk;1{sch}||schematic|1021415734000|1047947171000||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNPX-9;Y-13.5;)I2|ATTR_W(D5G1;HNPX-8.5;Y-12.5;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-16.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-17.75;)I0|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) gnd N W='$(W)' L='$(L)' AD='2*$(W)*hdifn/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifn/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifn/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifn/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
INMOSfwk;1{ic}|NMOSfwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_M(T)I1
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||6|-16.5||||
NOff-Page|conn@1||4.5|0||||
NOff-Page|conn@2||-10|-8||||
NGround|gnd@0||5|-11||||
N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5G1;OJ)S"P(\"L\")"|ATTR_width(D5G1.5;OJX0.5;Y-1;)S"P(\"W\")"
NWire_Pin|pin@0||0|-16.5||||
NWire_Pin|pin@1||0|0||||
Ngeneric:Invisible-Pin|pin@2||0|8.5|||||ART_message(D5G6;)S[NMOSfwk]
Awire|net@0|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
Awire|net@1|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
Awire|net@3|||1800|conn@2|y|-8|-8|nmos4p@0|g|-3|-8
Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
Ed||D5G2;|conn@1|y|B
Eg||D5G2;|conn@2|a|I
Es||D5G2;|conn@0|y|B
X
# Cell PMOS4f;1{ic}
CPMOS4f;1{ic}||artwork|1021415734000|1085594334000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y2.5;)I0|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-2|0|1|1|||ART_color()I74
NPin|pin@0||-0.5|0.25|1|1|YRR|
NPin|pin@1||-0.5|0.75|1|1|YRR|
NPin|pin@2||-0.75|0.5|1|1|Y|
NPin|pin@3||0|0.5||||
Ngeneric:Invisible-Pin|pin@4||0|2||||
Ngeneric:Invisible-Pin|pin@5||0|0.5||||
Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
Nschematic:Bus_Pin|pin@7||-3|0|-2|-2||
NPin|pin@8||0|1||||
NPin|pin@9||-0.75|1|1|1||
NPin|pin@10||-0.75|-1|1|1||
NPin|pin@11||0|-1||||
NPin|pin@12||0|-2||||
NPin|pin@13||-3|0|||RR|
NPin|pin@14||-2.5|0|1|1|RR|
NPin|pin@15||0|2||||
NPin|pin@16||-1.5|-1|1|1||
NPin|pin@17||-1.5|1|1|1||
AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
AThicker|net@5|||FS1800|pin@13||-3|0|pin@14||-2.5|0|ART_color()I74
AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
AThicker|net@9|||FS900|pin@17||-1.5|1|pin@16||-1.5|-1|ART_color()I74
Eb||D5G1;|pin@5||B
Ed||D5G1;|pin@6||B
Eg||D5G1;|pin@7||I
Es||D5G1;|pin@4||B
X
# Cell PMOS4f;1{sch}
CPMOS4f;1{sch}||schematic|1021415734000|1098423419000||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y0.25;)I2|ATTR_W(D5G1;HNPX-8.75;Y2;)I3|ATTR_drain_shared(D5G1;HNPX-9;Y-3.25;)I0|ATTR_source_shared(D5G1;HNPX-9.5;Y-4.75;)I0|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOS4f;1{ic}|PMOS4f@0||20.75|16|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||5|11.5||||
NOff-Page|conn@1||5|8||||
NOff-Page|conn@2||-19|7||||
NOff-Page|conn@3||5|1||||
NWire_Pin|pin@0||0|11.5||||
NWire_Pin|pin@1||0|1||||
Ngeneric:Invisible-Pin|pin@2||-1|23|||||ART_message(D5G6;)S[pmos4]
Ngeneric:Invisible-Pin|pin@3||-1.5|19.5|||||ART_message(D5G2;)S[4 terminal PMOS device]
N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"
Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-17|7
Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
Eb||D5G2;|conn@1|y|B
Ed||D5G2;|conn@3|y|B
Eg||D5G2;|conn@2|a|I
Es||D5G2;|conn@0|y|B
X
# Cell PMOS4fwk;1{ic}
CPMOS4fwk;1{ic}||artwork|1021415734000|1098422023000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y2.5;)I0|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I74
Nschematic:Bus_Pin|pin@0||0|0.5|-2|-2||
NPin|pin@1||-0.75|0.5|1|1|Y|
NPin|pin@2||0|0.5||||
NPin|pin@3||-0.5|0.25|1|1|YRR|
NPin|pin@4||-0.75|0.5|1|1|Y|
NPin|pin@5||-0.5|0.75|1|1|YRR|
NPin|pin@6||-0.75|0.5|1|1|Y|
NPin|pin@7||-1.25|-0.75|1|1|Y|
NPin|pin@8||-1.25|0.75|1|1|Y|
NPin|pin@9||0|2||||
NPin|pin@10||-1.75|0|1|1|RRR|
NPin|pin@11||-3|0|||RR|
NPin|pin@12||0|-2||||
NPin|pin@13||0|-0.75||||
NPin|pin@14||-0.75|-0.75|1|1||
NPin|pin@15||-0.75|0.75|1|1||
NPin|pin@16||0|0.75||||
Nschematic:Bus_Pin|pin@17||-3|0|-2|-2||
Nschematic:Bus_Pin|pin@18||0|-2|-2|-2||
Ngeneric:Invisible-Pin|pin@19||0|2||||
Ngeneric:Invisible-Pin|pin@20||-0.5|0|||||ART_message(D5G1;)S[wk]
AThicker|net@0|||FS0|pin@2||0|0.5|pin@1||-0.75|0.5|ART_color()I74
AThicker|net@1|||FS3150|pin@3||-0.5|0.25|pin@4||-0.75|0.5|ART_color()I74
AThicker|net@2|||FS450|pin@5||-0.5|0.75|pin@6||-0.75|0.5|ART_color()I74
AThicker|net@3|||FS2700|pin@7||-1.25|-0.75|pin@8||-1.25|0.75|ART_color()I74
AThicker|net@4|||FS900|pin@15||-0.75|0.75|pin@14||-0.75|-0.75|ART_color()I74
AThicker|net@5|||FS900|pin@13||0|-0.75|pin@12||0|-2|ART_color()I74
AThicker|net@6|||FS2700|pin@16||0|0.75|pin@9||0|2|ART_color()I74
AThicker|net@7|||FS1800|pin@11||-3|0|pin@10||-1.75|0|ART_color()I74
AThicker|net@8|||FS1800|pin@14||-0.75|-0.75|pin@13||0|-0.75|ART_color()I74
AThicker|net@9|||FS0|pin@16||0|0.75|pin@15||-0.75|0.75|ART_color()I74
Eb||D5G1;|pin@0||B
Ed||D8G1;|pin@18||B
Eg||D6G1;|pin@17||I
Es||D2G1;|pin@19||B
X
# Cell PMOS4fwk;1{sch}
CPMOS4fwk;1{sch}||schematic|1021415734000|1098423662000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y1.25;)I2|ATTR_W(D5G1;HNPX-8.75;Y3;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-2.25;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-3.75;)I0|ATTR_SPICE_template(D5G1;NTX1.5;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-7.5;Y-10;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOS4fwk;1{ic}|PMOS4fwk@0||23.25|19.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||5|8||||
NOff-Page|conn@1||5|1||||
NOff-Page|conn@2||-8|7||||
NOff-Page|conn@3||5|11.5||||
Ngeneric:Invisible-Pin|pin@0||-1.5|19.5|||||ART_message(D5G2;)S[weak 4 terminal PMOS device]
Ngeneric:Invisible-Pin|pin@1||-1|23|||||ART_message(D5G6;)S[PMOSwk]
NWire_Pin|pin@2||0|1||||
NWire_Pin|pin@3||0|11.5||||
N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"|SIM_weak_node(D5G1;)SWeak
Awire|net@0|||1800|pmos4p@0|b|0|8|conn@0|a|3|8
Awire|net@1|||1800|conn@2|y|-6|7|pmos4p@0|g|-3|7
Awire|net@2|||2700|pin@2||0|1|pmos4p@0|d|0|5
Awire|net@3|||0|conn@1|a|3|1|pin@2||0|1
Awire|net@4|||2700|pmos4p@0|s|0|9|pin@3||0|11.5
Awire|net@5|||1800|pin@3||0|11.5|conn@3|a|3|11.5
Eb||D5G2;|conn@0|y|B
Ed||D5G2;|conn@1|y|B
Eg||D5G2;|conn@2|a|I
Es||D5G2;|conn@3|y|B
X
# Cell PMOSf;1{ic}
CPMOSf;1{ic}||artwork|1021415734000|1046821723000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y2.5;)I0|prototype_center()I[-8000,16000]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I74
Ngeneric:Invisible-Pin|pin@0||0|2||||
Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
NPin|pin@3||0|1||||
NPin|pin@4||-0.75|1|1|1||
NPin|pin@5||-0.75|-1|1|1||
NPin|pin@6||0|-1||||
NPin|pin@7||0|-2||||
NPin|pin@8||-3|0|||RR|
NPin|pin@9||-2.5|0|1|1|RRR|
NPin|pin@10||0|2||||
NPin|pin@11||-1.5|1|1|1|Y|
NPin|pin@12||-1.5|-1|1|1|Y|
AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I74
AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
AThicker|net@6|||FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I74
Ed||D8G1;|pin@1||B
Eg||D6G1;|pin@2||I
Es||D2G1;|pin@0||B
X
# Cell PMOSf;1{sch}
CPMOSf;1{sch}||schematic|1021415734000|1098422784000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y1.25;)I2|ATTR_W(D5G1;HNPX-8.75;Y3;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-1.75;)I0|ATTR_source_shared(D5G1;HNPX-8.5;Y-3.25;)I0|ATTR_SPICE_template(D5G1;NTX3;Y-10.5;)SM$(node_name) $(d) $(g) $(s) vdd P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-3.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOSf;1{ic}|PMOSf@0||30.25|21.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||8|12.5||||
NOff-Page|conn@1||-25|7||||
NOff-Page|conn@2||8.5|0||||
NWire_Pin|pin@0||0|12.5||||
NWire_Pin|pin@1||0|0||||
Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)S[PMOSf]
Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S[4 terminal lambda-based PMOS device]
N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"
NPower|pwr@0||6|8||||
Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-23|7
Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
Ed||D5G2;|conn@2|y|B
Eg||D5G2;|conn@1|a|I
Es||D5G2;|conn@0|y|B
X
# Cell PMOSfwk;1{ic}
CPMOSfwk;1{ic}||artwork|1021415734000|1047945019000|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNPX3.5;)I2|ATTR_W(D6G1;HNPX2;Y1;)I3|ATTR_drain_shared(D5G1;HPX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;HPX0.5;Y2.5;)I0|prototype_center()I[-8000,16000]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I74
Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
Ngeneric:Invisible-Pin|pin@1||0|2||||
Nschematic:Bus_Pin|pin@2||0|-2|-2|-2||
Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
NPin|pin@4||0|0.75||||
NPin|pin@5||-0.75|0.75|1|1||
NPin|pin@6||-0.75|-0.75|1|1||
NPin|pin@7||0|-0.75||||
NPin|pin@8||0|-2||||
NPin|pin@9||-3|0|||RR|
NPin|pin@10||-1.75|0|1|1|RRR|
NPin|pin@11||0|2||||
NPin|pin@12||-1.25|0.75|1|1|Y|
NPin|pin@13||-1.25|-0.75|1|1|Y|
AThicker|net@0|||FS0|pin@4||0|0.75|pin@5||-0.75|0.75|ART_color()I74
AThicker|net@1|||FS1800|pin@6||-0.75|-0.75|pin@7||0|-0.75|ART_color()I74
AThicker|net@2|||FS1800|pin@9||-3|0|pin@10||-1.75|0|ART_color()I74
AThicker|net@3|||FS2700|pin@4||0|0.75|pin@11||0|2|ART_color()I74
AThicker|net@4|||FS900|pin@7||0|-0.75|pin@8||0|-2|ART_color()I74
AThicker|net@5|||FS900|pin@5||-0.75|0.75|pin@6||-0.75|-0.75|ART_color()I74
AThicker|net@6|||FS2700|pin@13||-1.25|-0.75|pin@12||-1.25|0.75|ART_color()I74
Ed||D8G1;|pin@2||B
Eg||D6G1;|pin@3||I
Es||D2G1;|pin@1||B
X
# Cell PMOSfwk;1{sch}
CPMOSfwk;1{sch}||schematic|1021415734000|1098423644000||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5G1;HNPX-8.5;Y1.25;)I2|ATTR_W(D5G1;HNPX-8.75;Y3;)I3|ATTR_drain_shared(D5G1;HNPX-8.5;Y-2.25;)I0|ATTR_source_shared(D5G1;HNPX-9;Y-3.75;)I0|ATTR_SPICE_template(D5G1;NTX2.5;Y-12.5;)SM$(node_name) $(d) $(g) $(s) vdd P W='$(W)' L='$(L)' AD='2*$(W)*hdifp/0.1u/($(drain_shared)+1)' AS='2*$(W)*hdifp/0.1u/($(source_shared)+1)' PD='(2*$(W)+4*hdifp/0.1u)/($(drain_shared)+1)' PS='(2*$(W)+4*hdifp/0.1u)/($(source_shared)+1)'|ATTR_verilog_template(D5G1;NTX-2.5;Y-14.5;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
IPMOSfwk;1{ic}|PMOSfwk@0||27.25|16.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_M(T)I1
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||5|11.5||||
NOff-Page|conn@1||-8|7||||
NOff-Page|conn@2||5|1||||
NWire_Pin|pin@0||0|11.5||||
NWire_Pin|pin@1||0|1||||
Ngeneric:Invisible-Pin|pin@2||-1|23|||||ART_message(D5G6;)S[PMOSwk]
Ngeneric:Invisible-Pin|pin@3||-1.5|19.5|||||ART_message(D5G2;)S[4 terminal lambda-based weak PMOS device]
N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5G1;OJX1.5;)S"P(\"L\")"|ATTR_width(D5G1.5;OJX-0.5;Y-2;)S"P(\"W\")"
NPower|pwr@0||6|8||||
Awire|net@0|||1800|pin@0||0|11.5|conn@0|a|3|11.5
Awire|net@1|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
Awire|net@2|||0|conn@2|a|3|1|pin@1||0|1
Awire|net@3|||2700|pin@1||0|1|pmos4p@0|d|0|5
Awire|net@4|||1800|conn@1|y|-6|7|pmos4p@0|g|-3|7
Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
Ed||D5G2;|conn@2|y|B
Eg||D5G2;|conn@1|a|I
Es||D5G2;|conn@0|y|B
X
# Cell anOrangeGallery;1{sch}
CanOrangeGallery;1{sch}||schematic|1263074922138|1263221285099|
INMOS4f;1{ic}|NMOS4f@0||-12|-18|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
INMOS4fwk;1{ic}|NMOS4fwk@0||0|-18|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
INMOSf;1{ic}|NMOSf@0||-12|-6|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
INMOSfwk;1{ic}|NMOSfwk@0||0|-6|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y-2.5;)I0
IPMOS4f;1{ic}|PMOS4f@0||-12|18|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IPMOS4fwk;1{ic}|PMOS4fwk@0||0|18|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IPMOSf;1{ic}|PMOSf@0||-12|6|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
IPMOSfwk;1{ic}|PMOSfwk@0||0|6|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_drain_shared(D5G1;PX0.5;Y-2.5;)I0|ATTR_source_shared(D5G1;PX0.5;Y2.5;)I0
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@0||-1.5|25|||||ART_message(D5G4;)SanOrangeGallery
Iwire180;1{ic}|wire180@0||12|6|||D0G4;|ATTR_L(D5G1;PUD)I100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
Iwire;1{ic}|wire@0||12|-6|||D5G4;|ATTR_C(D5G1;NPUCY-2.5;)S0.020f|ATTR_L(D5G1;PUD)I100|ATTR_R(D5G1;NPURY-1.5;)S15m
X
# Cell wire;1{ic}
Cwire;1{ic}||artwork|1083964052000|1083971272000|E|ATTR_C(D5G1;HNPUCY-2.5;)S0.020f|ATTR_L(D5G1;HPUD)I100|ATTR_R(D5G1;HNPURY-1.5;)S15m|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
NThick-Circle|art@2||2|0|1.5|1.5|||ART_color()I74
NPin|pin@0||-2.75|0|1|1||
NPin|pin@1||-4|0||||
NPin|pin@2||2|0|1|1||
NPin|pin@3||4|0||||
NPin|pin@4||-2|0.75|1|1||
NPin|pin@5||2|0.75|1|1||
NPin|pin@6||2|-0.75|1|1||
NPin|pin@7||-2|-0.75|1|1||
Nschematic:Bus_Pin|pin@8||4|0|-2|-2||
Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
AThicker|net@0|||IJS0|pin@0||-2.75|0|pin@1||-4|0|ART_color()I74
AThicker|net@1|||IJS1800|pin@2||2|0|pin@3||4|0|ART_color()I74
AThicker|net@2|||IJS0|pin@5||2|0.75|pin@4||-2|0.75|ART_color()I74
AThicker|net@3|||IJS0|pin@6||2|-0.75|pin@7||-2|-0.75|ART_color()I74
Ea||D5G2;|pin@9||U
Eb||D5G2;|pin@8||U
X
# Cell wire;1{sch}
Cwire;1{sch}||schematic|1083961993000|1084405246000||ATTR_C(D5G1;HNPUCX-19;Y-9;)S0.020f|ATTR_L(D5G1;HNPUDX-19;Y-7;)I100|ATTR_R(D5G1;HNPURX-19;Y-8;)S15m|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||-10|0|||||SCHEM_capacitance(D5G1;OJUC)S@C*@L/3
NCapacitor|cap@1||10|0|||||SCHEM_capacitance(D5G1;OJUC)S@C*@L/3
NCapacitor|cap@2||0|0|||||SCHEM_capacitance(D5G1;OJUC)S@C*@L/3
NOff-Page|conn@0||21|4|||RR|
NOff-Page|conn@1||-21|4||||
NGround|gnd@0||0|-8||||
Ngeneric:Invisible-Pin|pin@0||15|7|||||ART_message(D5G1;)S[R2 ]
Ngeneric:Invisible-Pin|pin@1||-15|7|||||ART_message(D5G1;)S[R1 = @R*@L/6]
Ngeneric:Invisible-Pin|pin@2||0|7|||||ART_message(D5G1;)S[R12= @R*@L/3]
Ngeneric:Invisible-Pin|pin@3||16.5|-2|||||ART_message(D5G1;)S[C = @C*@L/3]
Ngeneric:Invisible-Pin|pin@4||0|14|||||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
Ngeneric:Invisible-Pin|pin@5||-1|22|||||ART_message(D5G6;)S[wire]
NWire_Pin|pin@6||0|-4||||
NWire_Pin|pin@7||10|-4||||
NWire_Pin|pin@8||-10|-4||||
NWire_Pin|pin@9||10|4||||
NWire_Pin|pin@10||0|4||||
NWire_Pin|pin@11||-10|4||||
NResistor|res@0||-15|4|||||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/6
NResistor|res@1||-5|4|||||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/3
NResistor|res@2||15|4|||||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/6
NResistor|res@3||5|4|||||SCHEM_resistance(D5G1;OJURY1.5;)S@R*@L/3
Iwire;1{ic}|wire@0||15|24|||D0G4;|ATTR_C(D5G1;NPUCY-2.5;)F2.23E-16|ATTR_L(D5G1;PUD)I100|ATTR_R(D5G1;NPURY-1.5;)F0.24
Awire|net@0|||IJS1800|res@2|b|17|4|conn@0|y|19|4
Awire|net@1|||IJS0|res@0|a|-17|4|conn@1|y|-19|4
Awire|net@2|||IJS900|pin@6||0|-4|gnd@0||0|-6
Awire|net@3|||IJS2700|pin@6||0|-4|cap@2|b|0|-2
Awire|net@4|||IJS0|pin@7||10|-4|pin@6||0|-4
Awire|net@5|||IJS0|pin@6||0|-4|pin@8||-10|-4
Awire|net@6|||IJS900|cap@1|b|10|-2|pin@7||10|-4
Awire|net@7|||IJS2700|pin@8||-10|-4|cap@0|b|-10|-2
Awire|net@8|||IJS900|pin@9||10|4|cap@1|a|10|2
Awire|net@9|||IJS0|res@2|a|13|4|pin@9||10|4
Awire|net@10|||IJS0|pin@9||10|4|res@3|b|7|4
Awire|net@11|||IJS900|pin@10||0|4|cap@2|a|0|2
Awire|net@12|||IJS0|res@3|a|3|4|pin@10||0|4
Awire|net@13|||IJS0|pin@10||0|4|res@1|b|-3|4
Awire|net@14|||IJS900|pin@11||-10|4|cap@0|a|-10|2
Awire|net@15|||IJS0|res@1|a|-7|4|pin@11||-10|4
Awire|net@16|||IJS0|pin@11||-10|4|res@0|b|-13|4
Ea||D4G2;|conn@1|a|U
Eb||D6G2;X-5;|conn@0|y|U
X
# Cell wire180;1{ic}
Cwire180;1{ic}||artwork|1083966364000|1084405602000|E|ATTR_L(D5G1;HPUD)I100|ATTR_LEWIRE(D5G1;HPT)I1|ATTR_layer(D5G1;HNPY-1;)I1|ATTR_width(D5G1;HNPY-2;)I3|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-1.75|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
NThick-Circle|art@2||1.75|0|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
NPin|pin@0||-1.75|0.75|1|1||
NPin|pin@1||1.75|0.75|1|1||
NPin|pin@2||1.75|-0.75|1|1||
NPin|pin@3||-1.75|-0.75|1|1||
Nschematic:Bus_Pin|pin@4||2.5|0|-1|-1||
Nschematic:Bus_Pin|pin@5||-2.5|0|-1|-1||
AThicker|net@0|||FS0|pin@1||1.75|0.75|pin@0||-1.75|0.75|ART_color()I74
AThicker|net@1|||FS0|pin@2||1.75|-0.75|pin@3||-1.75|-0.75|ART_color()I74
Ea||D5G2;|pin@5||B
Eb||D5G2;|pin@4||B
X
# Cell wire180;1{sch}
Cwire180;1{sch}||schematic|1083965121000|1119463992509||ATTR_L(D5G1;HNPUDX-20.5;Y-6.5;)I100|ATTR_LEWIRE(D5G1;HNPTX-20.5;Y-9.5;)I1|ATTR_layer(D5G1;HNPX-20.5;Y-7.5;)I1|ATTR_width(D5G1;HNPX-20.5;Y-8.5;)I3|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-23|-1||||
NOff-Page|conn@1||-5.5|-1|||YRR|
Ngeneric:Invisible-Pin|pin@0||-5.5|9.5|||||ART_message(BD5G2;)S[wire180]
Ngeneric:Invisible-Pin|pin@1||7|-8|||||ART_message(D5G1;)SR = (@layer==0?5:0.045)/@width
Ngeneric:Invisible-Pin|pin@2||7|-6|||||ART_message(D5G1;)SC = [(@layer==0?15:20)+(@width-3)] aF/lambda
Ngeneric:Invisible-Pin|pin@3||-14|6|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 180nm tech"]
Ngeneric:Invisible-Pin|pin@4||-10|3.5|||||ART_message(D6G1;)Slayer=0 is for poly
Ngeneric:Invisible-Pin|pin@5||7|-10|||||ART_message(D5G1;)SLEWIRECAP = C * L
Iwire180;1{ic}|wire180@0||14|7.88|||D0G4;|ATTR_L(D5G1;PUD)I100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
Iwire;1{ic}|wire@0||-15|-1|||D0G4;|ATTR_C(D5G1;NOJPUCY-2.5;)S((@layer==0?15:20)+(@width-3))*1e-18|ATTR_L(D5G1;OJPUD)S@L|ATTR_R(D5G1;NOJPURY-1.5;)S(@layer==0?5:0.045)/@width|ATTR_LEWIRECAP(D5G1;NOJTUDX-5.5;Y-9.5;)S((@layer==0?15:20)+(@width-3))*1e-18*@L
Awire|net@0|||0|wire@0|a|-19|-1|conn@0|y|-21|-1
Awire|net@1|||1800|wire@0|b|-11|-1|conn@1|y|-7.5|-1
Ea||D4G2;|conn@0|a|B
Eb||D4G2;|conn@1|a|B
X
