jnr.a64asm.INST_CODE Maven / Gradle / Ivy

/*
 * Copyright (C) 2018 Ossdev07
 *
 * This file is part of the JNR project.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *    http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */



package jnr.a64asm;

public enum INST_CODE {

    INST_ADC_ADDSUB_CARRY,
    INST_ADCS_ADDSUB_CARRY,
    INST_ADD_ADDSUB_IMM,
    INST_ADD_ADDSUB_IMM_SP,
    INST_ADD_ADDSUB_SHIFT,
    INST_ADD_EXT_ADDSUB_EXT,
    INST_ADDS_ADDSUB_EXT,
    INST_ADDS_ADDSUB_SHIFT,
    INST_ADDS_ADDSUB_IMM,
    INST_ADR_PCRELADDR,
    INST_ADRP_PCRELADDR,
    INST_AND_LOG_IMM,
    INST_AND_LOG_SHIFT,
    INST_ANDS_LOG_IMM,
    INST_ANDS_LOG_SHIFT,
    INST_ASR_BITFIELD,
    INST_ASR_DP_2SRC,
    INST_ASRV_DP_2SRC,
    INST_AT_IC_SYSTEM,
    INST_B_C_CONDBRANCH,
    INST_B_BRANCH_IMM,
    INST_BCC_CONDBRANCH,
    INST_BCS_CONDBRANCH,
    INST_BEQ_CONDBRANCH,
    INST_BFI_BITFIELD,
    INST_BFM_BITFIELD,
    INST_BFXIL_BITFIELD,
    INST_BGE_CONDBRANCH,
    INST_BGT_CONDBRANCH,
    INST_BHI_CONDBRANCH,
    INST_BHS_CONDBRANCH,
    INST_BIC_LOG_IMM,
    INST_BIC_LOG_SHIFT,
    INST_BICS_LOG_SHIFT,
    INST_BL_BRANCH_IMM,
    INST_BLE_CONDBRANCH,
    INST_BLO_CONDBRANCH,
    INST_BLR_BRANCH_REG,
    INST_BLS_CONDBRANCH,
    INST_BLT_CONDBRANCH,
    INST_BMI_CONDBRANCH,
    INST_BNE_CONDBRANCH,
    INST_BPL_CONDBRANCH,
    INST_BR_BRANCH_REG,
    INST_BRK_EXCEPTION,
    INST_BVC_CONDBRANCH,
    INST_BVS_CONDBRANCH,
    INST_CBNZ_COMPBRANCH,
    INST_CBZ_COMPBRANCH,
    INST_CCMN_CONDCMP_IMM,
    INST_CCMN_CONDCMP_REG,
    INST_CCMP_CONDCMP_IMM,
    INST_CCMP_CONDCMP_REG,
    INST_CINC_CONDSEL,
    INST_CINV_CONDSEL,
    INST_CLREX_IC_SYSTEM,
    INST_CLS_DP_1SRC,
    INST_CLZ_DP_1SRC,
    INST_CMN_ADDSUB_EXT,
    INST_CMN_ADDSUB_IMM,
    INST_CMN_ADDSUB_SHIFT,
    INST_CMP_ADDSUB_EXT,
    INST_CMP_ADDSUB_IMM,
    INST_CMP_ADDSUB_SHIFT,
    INST_CNEG_CONDSEL,
    INST_CSEL_CONDSEL,
    INST_CSET_CONDSEL,
    INST_CSETM_CONDSEL,
    INST_CSINC_CONDSEL,
    INST_CSINV_CONDSEL,
    INST_CSNEG_CONDSEL,
    INST_DC_IC_SYSTEM,
    INST_DCPS1_EXCEPTION,
    INST_DCPS2_EXCEPTION,
    INST_DCPS3_EXCEPTION,
    INST_DMB_IC_SYSTEM,
    INST_DRPS_BRANCH_REG,
    INST_DSB_IC_SYSTEM,
    INST_EON_LOG_SHIFT,
    INST_EOR_LOG_IMM,
    INST_EOR_LOG_SHIFT,
    INST_ERET_BRANCH_REG,
    INST_EXTR_EXTRACT,
    INST_HINT_IC_SYSTEM,
    INST_HLT_EXCEPTION,
    INST_HVC_EXCEPTION,
    INST_IC_IC_SYSTEM,
    INST_ISB_IC_SYSTEM,
    INST_LDAR_LDSTEXCL,
    INST_LDARB_LDSTEXCL,
    INST_LDARH_LDSTEXCL,
    INST_LDAXP_LDSTEXCL,
    INST_LDAXR_LDSTEXCL,
    INST_LDAXRB_LDSTEXCL,
    INST_LDAXRH_LDSTEXCL,
    INST_LDNP_LDSTNAPAIR_OFFS,
    INST_LDNP_LDSTNAPAIR_OFFS_V,
    INST_LDP_POST_INDEXED_IDST_IMM9,
    INST_LDP_PRE_INDEXED_IDST_IMM9,
    INST_LDP_LDSTPAIR_INDEXED_V,
    INST_LDP_LDSTPAIR_OFF_LDST_POS,
    INST_LDP_LDSTPAIR_OFF_V,
    INST_LDPSW_POST_INDEXED,
    INST_LDPSW_PRE_INDEXED,
    INST_LDPSW_OFF,
    INST_LDR_IMM_POST,
    INST_LDR_IMM_OFF,
    INST_LDR_REG,
    INST_LDR_IMM_PRE,
    INST_LDR_LOADLIT,
    INST_LDRB_IMM_POST,
    INST_LDRB_IMM_PRE,
    INST_LDRB_IMM_OFF,
    INST_LDRB_REG,
    INST_LDRH_IMM_POST,
    INST_LDRH_IMM_PRE,
    INST_LDRH_IMM_OFF,
    INST_LDRH_REG,
    INST_LDRSB_IMM_POST,
    INST_LDRSB_IMM_PRE,
    INST_LDRSB_IMM_OFF,
    INST_LDRSB_REG,
    INST_LDRSH_IMM_POST,
    INST_LDRSH_IMM_PRE,
    INST_LDRSH_IMM_OFF,
    INST_LDRSH_REG,
    INST_LDRSW_IMM_POST,
    INST_LDRSW_IMM_PRE,
    INST_LDRSW_IMM_OFF,
    INST_LDRSW_REG,
    INST_LDRSW_LOADLIT,
    INST_LDTR_LDST_UNPRIV,
    INST_LDTRB_LDST_UNPRIV,
    INST_LDTRH_LDST_UNPRIV,
    INST_LDTRSB_LDST_UNPRIV,
    INST_LDTRSH_LDST_UNPRIV,
    INST_LDTRSW_LDST_UNPRIV,
    INST_LDUR_LDST_UNSCALED,
    INST_LDUR_LDST_UNSCALED_X,
    INST_LDURB_LDST_UNSCALED,
    INST_LDURH_LDST_UNSCALED,
    INST_LDURSB_LDST_UNSCALED,
    INST_LDURSH_LDST_UNSCALED,
    INST_LDURSW_LDST_UNSCALED,
    INST_LDXP_LDSTEXCL,
    INST_LDXR_LDSTEXCL,
    INST_LDXRB_LDSTEXCL,
    INST_LDXRH_LDSTEXCL,
    INST_LSL_BITFIELD,
    INST_LSL_DP_2SRC,
    INST_LSLV_DP_2SRC,
    INST_LSR_BITFIELD,
    INST_LSR_DP_2SRC,
    INST_LSRV_DP_2SRC,
    INST_MADD_DP_3SRC,
    INST_MNEG_DP_3SRC,
    INST_MOV_ADDSUB_IMM,
    INST_MOV_LOG_IMM,
    INST_MOV_LOG_SHIFT,
    INST_MOV_MOVEWIDE,
    INST_MOV_MOVEWIDE_X,
    INST_MOVK_MOVEWIDE,
    INST_MOVN_MOVEWIDE,
    INST_MOVZ_MOVEWIDE,
    INST_MRS_IC_SYSTEM,
    INST_MSR_IC_SYSTEM,
    INST_MSR_IC_SYSTEM_X,
    INST_MSUB_DP_3SRC,
    INST_MUL_DP_3SRC,
    INST_MVN_LOG_SHIFT,
    INST_NEG_ADDSUB_SHIFT,
    INST_NEGS_ADDSUB_SHIFT,
    INST_NGC_ADDSUB_CARRY,
    INST_NGCS_ADDSUB_CARRY,
    INST_NOP_IC_SYSTEM,
    INST_ORN_LOG_SHIFT,
    INST_ORR_LOG_IMM,
    INST_ORR_LOG_SHIFT,
    INST_PRFM_LDST_POS__IMMEDIATE,
    INST_PRFM_LDST_REGOFF__REGISTER,
    INST_PRFM_LDST_UNSCALED,
    INST_PRFM_LOADLIT__LITERAL,
    INST_PRFUM_LDST_UNSCALED,
    INST_RBIT_DP_1SRC,
    INST_RET_BRANCH_REG,
    INST_REV_DP_1SRC,
    INST_REV_DP_1SRC_X,
    INST_REV16_DP_1SRC,
    INST_REV32_DP_1SRC,
    INST_ROR_DP_2SRC,
    INST_ROR_EXTRACT,
    INST_RORV_DP_2SRC,
    INST_SBC_ADDSUB_CARRY,
    INST_SBCS_ADDSUB_CARRY,
    INST_SBFIZ_BITFIELD,
    INST_SBFM_BITFIELD,
    INST_SBFX_BITFIELD,
    INST_SDIV_DP_2SRC,
    INST_SEV_IC_SYSTEM,
    INST_SEVL_IC_SYSTEM,
    INST_SMADDL_DP_3SRC,
    INST_SMC_EXCEPTION,
    INST_SMNEGL_DP_3SRC,
    INST_SMSUBL_DP_3SRC,
    INST_SMULH_DP_3SRC,
    INST_SMULL_DP_3SRC,
    INST_STLR_LDSTEXCL,
    INST_STLRB_LDSTEXCL,
    INST_STLRH_LDSTEXCL,
    INST_STLXP_LDSTEXCL,
    INST_STLXR_LDSTEXCL,
    INST_STLXRB_LDSTEXCL,
    INST_STLXRH_LDSTEXCL,
    INST_STNP_LDSTNAPAIR_OFFS,
    INST_STNP_LDSTNAPAIR_OFFS_X,
    INST_STP_LDSTPAIR_INDEXED_POST,
    INST_STP_LDSTPAIR_INDEXED_PRE,
    INST_STP_LDSTPAIR_OFF,
    INST_STR_LDST_IMM9_PRE,
    INST_STR_LDST_IMM9_POST,
    INST_STR_LDST_POS,
    INST_STR_LDST_REGOFF,
    INST_STRB_LDST_IMM9_POST,
    INST_STRB_LDST_OFFSET,
    INST_STRB_LDST_REGOFF,
    INST_STRB_LDST_PRE,
    INST_STRH_LDST_IMM_PRE,
    INST_STRH_LDST_IMM_POST,
    INST_STRH_LDST_IMM_OFF,
    INST_STRH_LDST_REGOFF,
    INST_STTR_LDST_UNPRIV,
    INST_STTRB_LDST_UNPRIV,
    INST_STTRH_LDST_UNPRIV,
    INST_STUR_LDST_UNSCALED,
    INST_STUR_LDST_UNSCALED_X,
    INST_STURB_LDST_UNSCALED,
    INST_STURH_LDST_UNSCALED,
    INST_STXP_LDSTEXCL,
    INST_STXR_LDSTEXCL,
    INST_STXRB_LDSTEXCL,
    INST_STXRH_LDSTEXCL,
    INST_SUB_ADDSUB_EXT,
    INST_SUB_ADDSUB_IMM,
    INST_SUB_ADDSUB_SHIFT,
    INST_SUBS_ADDSUB_EXT,
    INST_SUBS_ADDSUB_IMM,
    INST_SUBS_ADDSUB_SHIFT,
    INST_SVC_EXCEPTION,
    INST_SXTB_BITFIELD,
    INST_SXTH_BITFIELD,
    INST_SXTW_BITFIELD,
    INST_SYS_IC_SYSTEM,
    INST_SYSL_IC_SYSTEM,
    INST_TBNZ_TESTBRANCH,
    INST_TBZ_TESTBRANCH,
    INST_TLBI_IC_SYSTEM,
    INST_TST_LOG_IMM,
    INST_TST_LOG_SHIFT,
    INST_UBFIZ_BITFIELD,
    INST_UBFM_BITFIELD,
    INST_UBFX_BITFIELD,
    INST_UDIV_DP_2SRC,
    INST_UMADDL_DP_3SRC,
    INST_UMNEGL_DP_3SRC,
    INST_UMSUBL_DP_3SRC,
    INST_UMULH_DP_3SRC,
    INST_UMULL_DP_3SRC,
    INST_UXTB_BITFIELD,
    INST_UXTH_BITFIELD,
    INST_UXTW_LOG_SHIFT,
    INST_WFE_IC_SYSTEM,
    INST_WFI_IC_SYSTEM,
    INST_YIELD_IC_SYSTEM;

    public static final INST_CODE valueOf(int idx) {
        return values()[idx];
    }
}