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cvc5-cvc5-1.2.0.test.regress.cli.regress1.sygus.fwd-decl-2.sy Maven / Gradle / Ivy

; EXPECT: feasible
; COMMAND-LINE: --sygus-out=status
(set-logic ALL)
(synth-fun g ((x Int) (y Int)) Int
  ((Start Int))
  (
  (Start Int ((- Start Start) x y))
  )
)
(synth-fun f ((x Int) (y Int)) Int
  ((Start Int))
  (
  (Start Int ((g x y) (+ Start Start) x y))
  )
)
(constraint (= (f 3 4) 1))
(constraint (= (f 2 7) 5))
(check-synth)